Silicon Valley Area Chapter

(SCV, SF, OEB)

Learn about advances in device packaging designs, methods, materials, processes and reliability

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Learn about advances in device packaging designs, methods, materials, processes and reliability

Learn about advances in device packaging designs, methods, materials, processes and reliability

Upcoming Meetings and Webinars

Chiplet-in-Wafer Technology for the Development of III-V RF ICs (F. Herrault) — 5G, radar, compound semiconductors, co-integration, packaging solutions, in passive wafer interconnects …
Scheduled ical Google outlook
(on the Internet)
Growth in Semiconductor Packaging and Assembly: Are We in Another “Roaring 20s”? (Vardaman) — continued expansion, drivers, shortages, application areas …
Scheduled ical Google outlook
(on the Internet)
Dr. Ivor Barber of AMD presenting at one of our luncheon talks.

Dr. Ivor Barber of AMD presenting at one of our luncheon talks.

Upcoming Conferences and Workshops

Slides and Webinars from Past Meetings

Advanced Packaging for Silicon Photonics Based Modules and Applications (Bernabé) -- packaging techniques, mass manufacturing, reliability, complexity, scalability, cost ...
Scheduled
(on the Internet)
Integration of an Optoelectronic, Flexible Neural Stimulator for Implantable Retinal Prosthesis (Yu-Hsin Liu) -- replace photoreceptors, neural stimulating array, flex substrate, silicon dielets, testing results ...
Scheduled
(on the Internet)
Ultrafast Time Domain Cryogenic CMOS Device Characterization Platform for Quantum Computing Applications (Pragya Shrestha) -- cryo-CMOS, electronic functionality, device technology, low-temp models, low-power, measurements ...
Scheduled
(on the Internet)
Package Technology, Design, and Methodology Challenges and Solutions for High Bandwidth Electronic Systems (Kemal Aygun) -- interchip, IO bandwidth, fan-out, 2.5D packaging, design, simulation, analysis, validation ...
Scheduled
(on the Internet)
Hardware Reliability Qualification of Robo-Taxi: Environmental Stress and Failure Modes for Autonomous Vehicle Modules/Components (Fen Chen) -- self-driving profiles, stresses, approaches, analysis, low-sample testing, failure examples ...
Scheduled
(on the Internet)
Use of Flash Lamps to Achieve Non-equilibrium Soldering and Assembly using Conventional Solder Alloys (Rudy Ghosh) -- anisotropic adhesives, alloys, fluxes, wearables, fabrics, results ...
Scheduled
(on the Internet)
Scalable Highly-Integrated Photonics Packaging for the 5G World: From Datacenters to Drones (Jeroen Duis) -- photonics motherboard, dissimilar components, hybrid integration, thermal management ...
Scheduled
(on the Internet)
Bonding Technology for the Next Generation Integration Schemes (Jurgen Burggraf) -- die shrink, yield, heterogeneous chips, interconnect challenges, wafer bonding ...
Scheduled
(on the Internet)

An advanced pre-production package, held by UC-Davis graduate A. Nguyen, a packaging engineer

Message from Chapter Chair, Annette Teng

Annette Teng

Annette Teng

    Welcome, and thank you for visiting our IEEE-EPS-Silicon Valley Chapter website. Whether you are IEEE member or casual onlooker, we hope you can enjoy our website and find us of value to you.

   Since our inception over 50 years ago, EPS-SCV has provided a valuable forum for those who are interested in learning and exchanging knowledge relating to electronic packaging design, assembly, test, thermal and stress management. Our chapter is a facilitator for sharing knowledge and networking with others through activities such as lunch talks, symposiums and factory visits. We normally hold a monthly lunch seminar at SEMI Headquarters in Milpitas. However, since the shelter-in-place came into effect, we have organized a series of EPS webinars in the area of device package heterogeneous integration and the HI Roadmap. Slides and videos from past seminars can be downloaded/viewed from this webpage. Membership is not required to attend nor required to download/view past content. We are in various stages of organizing more webinars and virtual symposiums for the rest of this year.

    Our last face to face seminar was on Feb 28, 2020 with a talk by John Lau, and our last symposium was Feb 20, 2020 — the Third Annual Heterogeneous Integration Roadmap (HIR) Symposium, with 170 attendees. Thankfully, no one was infected from attending either event.

    Our membership is made up of a few hundred Bay Area members who are currently employed or have previously worked in high tech firms (and academia) in the area of device packaging. Those of us keeping the chapter active consist of a committee of officers who are voted in yearly. If interested, you can become an IEEE-EPS member by going to the EPS Website; also, we have many opportunities within the chapter for you to get involved — such as outreach programs to promote packaging interests to students and also to provide funding to underserved groups.