Upcoming Meetings and Webinars Glass-Core Packaging and Its Reliability (Lau) -- interposer, thru vias, 2.5D, 3D, CTE, redistribution layers, outlook ...
(at SEMI, Milpitas)
Co-Packaged Optical Transceivers for HPC, Data Center and AI Applications (Kuchta) -- fiber optics, co-packaging, VCSEL, SiPh, HPC, data center, AI applications, requirements ...
(on the Internet)
Visit our Program Committee Page Upcoming Conferences and Workshops Symposium on Reliability for Electronics and Photonics Packaging (REPP) -- Reliability, Failure Modes and Testing for Integration of Electronics and Photonics (SiPh) ...
UCLA (and on the Internet)
Message from Past Chapter Chair, Annette Teng Since our inception over 50 years ago, EPS-SCV has provided a valuable forum for those who are interested in learning and exchanging knowledge relating to electronic packaging design, assembly, test, thermal and stress management. Our chapter is a facilitator for sharing knowledge and networking with others through activities such as lunch talks, symposiums and factory visits. We normally hold a monthly lunch seminar at SEMI Headquarters in Milpitas. However, since the shelter-in-place came into effect, we have organized a series of EPS webinars in the area of device package heterogeneous integration and the HI Roadmap. Slides and videos from past seminars can be downloaded/viewed from this webpage. Membership is not required to attend nor required to download/view past content. We are in various stages of organizing more webinars and virtual symposiums for the rest of this year. Our last face to face seminar was on Feb 28, 2020 with a talk by John Lau, and our last symposium was Feb 20, 2020 — the Third Annual Heterogeneous Integration Roadmap (HIR) Symposium, with 170 attendees. Thankfully, no one was infected from attending either event. Our membership is made up of a few hundred Bay Area members who are currently employed or have previously worked in high tech firms (and academia) in the area of device packaging. Those of us keeping the chapter active consist of a committee of officers who are voted in yearly. If interested, you can become an IEEE-EPS member by going to the EPS Website; also, we have many opportunities within the chapter for you to get involved — such as outreach programs to promote packaging interests to students and also to provide funding to underserved groups. |
Slides and Webinars from Past Meetings: Characterization and Application of a New Chip-Level Air Pump (Tarter) -- thermal management, air movement, static pressure, small ducts, µCooling, MEMS ...
(on the Internet)
AI-Enhanced Multimodal Approaches for Electronics Metrology and Failure Analysis (Asadi) -- microbumps, RDLs, inspection framework, machine learning, benchmark datasets, model training ...
(on the Internet)
The Evolution and Emerging role of Solder Joints in AI and High-Performance Electronics (TK Lee) -- Sn-Pb, SAC305, stresses, degradation mechanisms, new systems, challenges ...
(on the Internet)
Electronics Packaging Tutorials
An advanced pre-production package, held by UC-Davis graduate A. Nguyen, a packaging engineer |
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IEEE Santa Clara Valley Chapter, EPS
Serving Silicon Valley and the SF Bay Area
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