Speaker: Tae-Kyu Lee, Sr. Technical Leader, System Packaging and Reliability Center, Cisco Systems
Meeting Date: Thursday, October 23, 2025
Time: Checkin via WebEx at 11:50 AM; Presentation at 12:00 noon (PST)
Cost: none
Reservations: events.vtools.ieee.org/m/501073
Summary: For over three decades, Sn-based material solder joints have remained the silent workhorses of electronic packaging. Since the transition from eutectic Sn-Pb to SAC305 alloy systems, these interconnects have sustained the fast-moving pace of system- and device-level integration with sufficient mechanical, thermal, and electrical reliability. While the semiconductor industry has undergone unprecedented transformation toward higher performance systems, the SAC305 alloy solder joints have quietly absorbed stress, ensured functionality, and maintained manufacturability across generations of products.
However, the emergence of high-performance computing (HPC) and AI-driven network systems places unprecedented demands on these long-serving SAC305 interconnects. Are we asking too much from the long pasting current solder material and technology that has already given so much? This seminar revisits the fundamentals of solder joint evolution, exploring why it has been so effective for thirty years and the inherent limitations now emerging. The general thermo-mechanical and electrical performance degradation mechanism will be reviewed, and compared with the new material systems such as low melting temperature alloy systems. The lessons between these different degradation mechanisms and further demand and new boundary conditions will provide a view of what solder challenges in the AI era might look like. We will discuss whether the era of traditional solder joints is approaching its boundary of service, and what emerging roles solder might play. Looking forward, we will consider how interconnects must adapt or be reimagined to meet the challenges of the next generation of AI and High-Performance computing systems.
Bio: Dr. Tae-Kyu Lee is a Senior Technical Leader in the System Packaging and Reliability center (SPARC) in the Cisco Common Hardware Group (CHG) in San Jose, California. He served more than 20 years in the industry and academia on micro-electronics materials reliability, solder and interconnect stability, failure analysis and degradation mechanisms, advanced packaging, superconductor, metallurgy and metal additive manufacturing. He received his Ph.D. degree in Materials Science and Engineering at University of California, Berkeley in 2004. Before joining the Cisco Technology and Quality (TnQ) group in 2006, he was a post-doc in the Lawrence Berkeley National Laboratory (LBNL) and served as an Associate professor in the Department of Mechanical and Materials engineering at Portland State University from 2015 to 2021 before rejoining Cisco. He is an active member in TMS, SMTA, IEEE-ECTC and serves as an associate editor for the Journal of Electronic Materials. He has more than 3,000 citations on authored and co-authored peer-reviewed publications including a book and book chapters on solder interconnect, reliability and microstructure evolution. He is also a recipient of a TMS Functional material division Distinguished Service award.
