Silicon Valley Area Chapter


Design and Analysis of Chiplet Interfaces for Heterogeneous Systems 🗓

(Wendem Beyene) -- mixed technologies/nodes, parallel interconnects, power domains, supply noise, timing jitter ...

Speaker: Wendem Tsegaye Beyene, EPS Distinguished Lecturer
Download PDFSlides: February 11, 2021     View Webinar (48:51 + Q&A)
Meeting Date: Thursday, February 11, 2021
Cost: none
Summary: The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power delivery paths between multiple independent power domains. Although the channels are very short and the I/O power can be reduced by an order of magnitude, the huge increase in the transient current in multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multi-die systems. This talk discusses the unique signal and power integrity challenges of chiplet interfaces.
Bio: Wendem Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. In the past, he was employed by IBM, Hewlett-Packard, Agilent Technologies and Rambus Inc. He also worked as a principal Engineer with Intel Corp. managing a team working on modeling and analysis of power-delivery and signaling systems of digital-core and mixed-signal I/O subsystems of FPGA chips. He is an elected Associate Fellow of the Ethiopian Academy of Sciences, and has been selected as a Distinguished Llecturer for IEEE EPS as well as for IEEE EMCS Society.

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