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Silicon Valley Area Chapter

(SCV, SF, OEB)

3D Heterogenous Integration; Hardware Technologies for Computing; NSF Funding 🗓

Free portions of SEMICON/West: talks, sessions, exhibits

This was a Special Session at SEMICON/West; please view the edited talks that interest you!
Speakers:
“A 3D Heterogenous Integration Future: Enabling Continued System-level Electronic Scaling”, Dr. Eric Beyne (IMEC)
    On-demand video: View Webinar (51:10 plus Q&A)
“The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design”, Prof. Subhasish Mitra (Stanford)
    On-demand video: View Webinar (47:35 +Q&A)
“Overview of Co-Design of Electronics Systems, and Proposal to NSF for Co-Design Funding for Universities”, Prof. Jose Schutt-Aine (UI-UC)
    On-demand video: View Webinar (28:35 + Q&A)

Meeting Date: Monday, July 11, 2022
Location: Moscone Center, Moscone South, Level 2, Room 203, San Francisco
Time: 9:00 AM – 5:00 PM (PDT)

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Home  |  Contact IEEE Santa Clara Vally Chapter, EPS  |  Accessibility  |  Privacy & Opting Out of Cookies  |  Nondiscrimination Policy

IEEE Santa Clara Valley Chapter, EPS
Serving Silicon Valley and the SF Bay Area
© Copyright 2020 IEEE – All rights reserved. Use of this Web site signifies your agreement to the IEEE Terms and Conditions.
A not-for-profit organization, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.