Top SoC Design Challenges – Panel

Date: Tuesday, April 8, 2014, 6:30 PM Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map) Panelists: Naresh Sehgal, Intel, SW Director for FPGA based Silicon platforms for Mobile products Paul McLellan, SemiWiki Project, Blogger & EDA Expert Tom Dillinger, Oracle, CAD Technology John Swan, Swan on Chips, SoC Technologist