IEEE Santa Clara Valley Chapter
January 21, 2010
January 21 2010: Our speaker was Prof. Elad Alon and the topic of his presentation was “Integrated Circuit Design with Nano-Electro-Mechanical Switches“.
Abstract
No matter how slowly they are allowed to run, digital logic gates implmented with CMOS transistors have a well-defined minimum energy that they must dissipate for each operation they perform. This minimum energy dissipation in CMOS can be traced back to the imperfection of transistors as switches – i.e., that their subthreshold slope is limited by kT/q. In contrast, switches based on mechanically making or breaking electrical contact can achieve zero leakage and infinite subthreshold slope, and hence may some day enable substantial improvements in energy efficiency. However, realizing this goal requires that the underlying circuits are tailored to the characteristics of these switches. Hence, in this talk I will describe such mechanical switch-optimized circuit architectures and then quantify the energy, performance, and area tradeoffs of these designs in comparison to CMOS.
Biography
Prof. Elad Alon received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University in 2001, 2002, and 2006, respectively. In Jan. 2007, he joined the University of California at Berkeley as an Assistant Professor of Electrical Engineering and Computer Sciences, where he is now a co-director of the Berkeley Wireless Research Center (BWRC). He has also held visiting positions at Intel, AMD, Rambus, Hewlett Packard, and IBM Research, where he worked on integrated circuits for a variety of applications using bulk and SOI processes from 130nm down to 32nm. His research focuses on the design and implementation of energy-efficient integrated systems and the circuits/technologies that comprise them.
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