Upcoming Events

Wednesday September 15, 2021, 6:00-7:00PM
Title:  “Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)
Location: Virtual Seminar Online
Registration Link: (Register Here)

Date & Time: Wednesday September 15, 2021, 6:00-7:00PM

Location: Virtual Seminar Online

The Zoom link will be accessed through your Eventbrite ticket.

Registration Link (Required) : Register Here

Registration Fee: FREE, Donation Requested


IEEE members – $2 donation

Non-members – $5 donation


When verifying large SoC designs, one needs to write SystemVerilog models for analog/mixed-signal blocks to comply with the digital verification flow, such as UVM. This talk addresses ways to extract those models automatically from circuits. The first approach is called structural modeling, mapping each device in the circuit to an equivalent model in SystemVerilog and connecting them up as they are in the original circuit. While this guarantees correct-by-construction models, the improvement in the simulation speed is limited due to the low abstraction level of the models. The second approach is called functional modeling, aiming to raise the abstraction level of the models. One can select a part of the circuit and map it to one of the predefined model templates to generate its functional model. Although it requires some manual inputs, the resulting models can deliver significantly faster and even more accurate simulations than the structural models. Question is, how many model templates would be necessary to model analog circuits? This talk shares my journey to answer this. I will use a pipelined analog-to-digital converter (ADC) example to demonstrate these different approaches.


Jaeha Kim is currently Professor at Seoul National University (SNU), Seoul, Korea, and his research interests include low-power mixed-signal circuits and their design methodologies. He founded Scientific Analog, Inc. in 2015, a company developing EDA tools for analog/mixed-signal modeling and simulation in SystemVerilog. He received the B.S. degree in electrical engineering from Seoul National University in 1997, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1999 and 2003, respectively. Prior to joining SNU, Prof. Kim was with Stanford University as Acting Assistant Professor, with Rambus, Inc. as Principal Engineer, and with Inter-university Semiconductor Research Center (ISRC) at SNU as Post-doctoral Researcher. Prof. Kim is a recipient of the Takuo Sugano Award for outstanding far-east paper at 2005 ISSCC and is cited as Top 100 Technology Leader of Korea in 2020 by the National Academy of Engineering of Korea.







Santa Clara Valley Chapter of the Solid State Circuits Society


October 2021

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“Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)

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