SoC Power Reduction and Management Techniques

 

Speaker: Stefan Rusu, Intel Corporation

Time: July 18th (Thursday) evening 6.00 pm-9.00pm.

 

Abstract:

CMOS process technology scaling has enabled higher feature integration in system-on-chip with multiple CPU and graphics cores and larger on-die caches. Reducing and managing power consumption is the most challenging task in today’s highly complex systems. In this tutorial, we will review power reduction and management techniques implemented in recent microprocessor and SoC designs, covering the entire spectrum from server to handheld applications. We will review flip-flop power optimization techniques, clock loading reduction, low-voltage operation, leakage reduction techniques, dynamic voltage and frequency scaling, and fine-grain power management techniques. Special attention will be devoted to adaptive circuit techniques that reduce the voltage and frequency design guard-bands. This tutorial includes recent innovations and practical examples from both industry and academic research.

 Bio:

Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience includes 23 years with Intel Corp. and 6 years at Sun Microsystems. Stefan has authored over 95 papers on VLSI circuit technology and holds 38 U.S. patents. He is an IEEE Fellow and a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences. Stefan is an elected member of the SSCS AdCom and served as an Associate Editor of the IEEE Journal of Solid-State Circuits between 2005 and 2015.

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Santa Clara Valley Chapter of the Solid State Circuits Society

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