November 19, 2020

Thursday November 19, 2020, 6:00-8:00PM
Title:  “Low-Spur PLL Architectures and Techniques”, Prof. Mike Chen, USC
Location: Virtual Seminar Online, This talk was previously given as a tutorial at the IEEE CICC 2020 Conference.
Registration Link:
(Register here)

Date & Time: Thursday November 19, 2020, 6:00-8:00PM

This talk was previously given as a tutorial at the IEEE CICC 2020 Conference.

Location: Virtual Seminar Online

The Online link will be sent to you prior to the seminar.

Registration Link (Required) :

Registration Fee: FREE, Donation Requested

IEEE members – $2 donation
Non-members – $5 donation


One key design objective of a frequency synthesizer is to minimize the spurious tones, as they can degrade the overall jitter performance or cause other unwanted system-level impairments. In this tutorial, we will examine the sources of the spurious tone generation in different PLL architectures and operation modes. We will overview several design techniques to mitigate the spurious tones. Lastly, we will go over several real PLL design examples that demonstrate low-spur performances.


Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degrees from University of California, Berkeley, in 2002 and 2006, all in electrical engineering. He is an associate professor in Electrical Engineering Department at University of Southern California (USC) and holds the Colleen and Roberto Padovani Early Career Chair position.

As a graduate student, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted in industry today for low-power high-speed analog-to-digital conversion products. After joining USC in 2011, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, frequency synthesizers, RF/mm-wave transceiver designs, analog circuit design automation, bio-inspired computing, non-uniformly sampled circuits and systems. From 2006 to 2010, he worked on mixed-signal and RF circuits for various wireless communication products at Atheros Communications (now Qualcomm).

Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) both in 2014, Analog Devices Outstanding Student Award for recognition in IC design in 2006 and UC Regents’ Fellowship at Berkeley in 2000. He also achieved an honorable mention in the Asian Pacific Mathematics Olympiad, 1994. Dr. Chen has been serving as an associate editor of the IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member in IEEE Solid-State Circuits Society conferences, notably the IEEE International Solid-State Circuits Conference (ISSCC), IEEE Symposium on VLSI Circuits, and IEEE Custom Integrated Circuits Conference (CICC).





Santa Clara Valley Chapter of the Solid State Circuits Society


September 2021

Next Meeting

“Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)

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