Solid State Circuits Society
IEEE Santa Clara Valley Chapter
Signal Integrity in High Speed Data Link
Short Course on Signal Integrity in High Speed Data Link
Speaker: Dr. Shahab Ardalan, San Jose State University
Abstract:
“There are two types of designers: Those who have signal-integrity problems and those who will.”
–Sun Microsystems
High speed designs continue to experience major technology advancements with parallel high-speed data links now in the 100 Gbps range. Therefore, the interconnect losses, frequency dependent channel characteristics and other timing parameters need to be understood and considered during the design phase.
The concept of signal integrity for high-speed circuits and high-speed data links will be covered in this tutorial. The course covers developing the skill of analyzing high speed circuits, and understanding signal integrity and the terminology associated with it. Loss compensation techniques will be discussed in this course, while interconnect modeling and loss are taking into consideration.
The outline for the tutorial is as follows:
1. Introduction to high-speed links
2. Introduction to signal integrity
3. Signal and Timing parameters
4. Transmission lines: cross-talk, loss and modeling
5. Channel loss and compensation (equalization)
6. Continuous Time Linear Equalizer (CTLE)
7. Decision Feedback Equalizer (DFE)
8. Pre-emphasis
9. Use case: challenges in PCIe 4.0 data link
Bio: Shahab Ardalan (M’02, SM’10) completed his B.Sc. at Amirkabir University of Technology, Iran in 1999, and his PhD degree at the University of Waterloo, Waterloo, Canada in 2007. Dr. Ardalan joined the analog mixed signal research and development group in Gennum Corp. in 2007 where he continued his research activities on low-power, low-voltage circuits for high speed data and video broadcasting. In 2010, Dr. Ardalan joined San Jose State University as an assistant professor and director of center for analog and mixed signal where he is teaching and conducting research on topics of analog and mixed signal integrated circuits and integrated circuit security.
Dr. Ardalan’s research has led to several publications including more than 15 IEEE papers. He is the recipient of the best paper award of ICUE’04 and the CMC Industrial Award from the strategic Microelectronic Council of ITAC in 2005. Dr. Ardalan held a postgraduate scholarship from the National Science and Engineering Research Council of Canada (NSERC) from 2004-2007 and NSERC post-doctoral fellowship award in 2010. He has been a member of technical and organizing committees for number IEEE conferences. He was a member of the IEEE Canada board of executives from 2004-2012 and chair of the Solid State Circuits Society chapter in Kitchener/Waterloo.
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