May 19, 2011

Speaker: Ajith Amerasekera

Title: Ultra Low Power Electronics in the Next Decade

Abstract: We are seeing a shift in electronic technology from centralized and high-touch to ubiquitous and low-touch. Semiconductors are enabling the development of intelligent systems that enable a more immersive environment expanding the role and applications of electronic technology. Driving this change is the availability of low-power electronics for wireless connectivity and performance processing. In the next decade, our ability to develop system-level solutions for energy management, delivery and consumption, will determine the extent to which the application space for electronic technology will grow. Power management techniques developed in the last decade have focused on process technology and circuit design techniques. As we move to distributed intelligent systems, power reductions of another few orders of magnitude are required. This talk looks at some of the key areas for innovation ranging from ultra-low power chips for personal and health technology to solutions for energy generation and delivery for autonomous systems.

The constraint for the development and deployment of autonomous systems is access to the energy sources. In most applications advances in battery technology together with some form of harvesting and storage will be possible provided the power requirements are low. The present battery technology roadmap has a 2x capacity improvement every decade, while the power demand will probably increase at the rate of 2x every 18 months or so. Key areas for innovation are in RF/analog, where achieving wireless connectivity with high data rates will be a challenge for low power, the need for more performance embedded processing, and the sensor technology, as well as the battery, energy generation, harvesting, and management. The next decade will see strong cross-functional design between multi-scale systems engineers, circuit designers, and software engineers.


Bio: Ajith Amerasekera is a TI Fellow and Director of the Kilby Research Labs at TI. After receiving his PhD in 1986 he worked at Philips Research Labs, Eindhoven, The Netherlands, on the first submicron semiconductor development. In 1991, he joined Texas Instruments, Dallas, working in the VLSI Design Labs on circuit and device modeling of high current effects in devices and circuits. Since 1999, he has been working on circuit design and IP development for TI’s CMOS technologies from 250nm to 32nm. Before taking up the role at the Kilby Labs, Ajith was Chief Technology Officer for TI’s ASIC Business Unit and Director of ASIC Technology Strategy. He has 28 issued patents, and has published over 100 papers in technical journals and conferences, in addition to 4 books on ICs and semiconductor device reliability. Ajith has served on the technical program committees of a number of International Conferences, and he was the Technical Program Chair of the 2010 VLSI Symposium on Circuits.



SCV SSCS Technical meetings are typically held on The THIRD Thursday of each month at:

National Semiconductor Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and NSC Map

Refreshments are provided at 6:00 PM and the talk typically begins at 6:30 PM.
Donations requested to partially cover food cost.

The talks are open to everyone, feel free to join us even if you are not an IEEE member yet



Santa Clara Valley Chapter of the Solid State Circuits Society


October 2021

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“Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)

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