Distinguished Lecturer Seminar: “Demystifying Linear Time Varying Circuits ” by Shanthi Pavan, IIT-Madras

Thursday Oct. 20, 2016, 6:00-8:00PM
Title:  “Demystifying Linear Time Varying Circuits” by Shanthi Pavan, Indian Institute of Technology-Madras
Location: Jack Gifford Event Center at Maxim Integrated Headquarters
160 Rio Robles, San Jose, CA
(Register here)



An analog/mixed-signal designer encounters time varying circuits everywhere – sample-and-holds, chopper stabilised amplifiers, mixers, switched-capacitor amplifiers and filters, discrete and continuous-time delta sigma modulators, N-path filters. The analysis of signals and noise in these circuits is often associated with messy mathematics and algebra.
This talk aims to demystify linear (periodically) time varying circuits. Starting from first principles, intuition behind various aspects of  time-varying circuits and systems  will be given. This intuition is illustrated with case studies of practical circuits and systems, like chopper-stabilised amplifiers and continuous-time delta-sigma modulators.


Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engg from the Indian Institute of Technology, Madras in 1995 and the Masters and Doctoral degrees from Columbia University, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras, where he is a Professor of Electrical Engineering. His research interests are in the areas of high speed analog circuit design and signal processing.


Dr.Pavan is the recipient of many awards for teaching and research, including the IEEE Circuits and Systems Society Darlington Best Paper Award  and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.


Eventbrite registration is mandatory for every one to attend the talk.


Jack Gifford Event Center at Maxim Integrated Headquarters, Building A (160 Rio Robles, San Jose, CA 95134 USA)

Time: October 20 (Thursday) evening 6:00pm-8.00pm.

Networking and Refreshments ($6 donation requested):  6:00 PM – 6:30 PM

Technical Talk/Q&A Session:  6.30 PM – 8.00 PM


Santa Clara Valley Chapter of the Solid State Circuits Society


September 2021

Next Meeting

“Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)

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