April 18, 2019

Thursday April 18, 2019, 6:00-8:00PM
Title:  “Plasticine: A Reconfigurable Dataflow Architecture for Machine Learning/Software 2.0”, Prof. Kunle Olukotun, Stanford University/SambaNova Systems, sponsored by Computer Society, CIS (Artificial Intelligence)
Location: Texas Instruments Silicon Valley Auditorium
2900 Semiconductor Dr., Building E, Santa Clara, CA 
(Register here)

Date & Time: Thursday April 18, 2019, 6:00-8:00PM

Location: Texas Instruments Building E Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051

Directions: TI-BldgE-Auditorium.pdf

Registration Link (Required) : https://www.eventbrite.com/e/plasticine-a-reconfigurable-dataflow-architecture-for-software-20-prof-kunle-olukotun-stanford-tickets-59974160328

Registration Fee: FREE, Donation Requested

IEEE members – $5 donation
Non-members – $5


The use of machine learning to generate models from data is replacing traditional software development for many applications. This fundamental shift in how we develop software, known as Software 2.0, has provided dramatic improvements in the quality and ease of deployment for these applications. The continued success and expansion of the Software 2.0 approach must be powered by the availability of powerful, efficient and flexible chips that are tailored for machine learning applications. This talk will describe a design approach that optimizes computer systems to match the requirements of machine learning applications. The full-stack design approach integrates machine learning algorithms that are optimized for the characteristics of applications and the strengths of modern hardware, domain-specific languages and advanced compilation technology designed for programmability and performance, and a reconfigurable dataflow architecture called Plasticine that achieve both high flexibility and high energy efficiency.
Plasticine is a new spatially reconfigurable architecture designed to efficiently execute applications composed of parallel patterns. I will describe the Plasticine architecture: the compute pipeline that exploits nested parallelism, the configurable memory system that captures data locality and sustains compute throughput with multiple banking modes, and the on-chip interconnect that supports communication at multiple levels of granularity.


Kunle Olukotun is the Cadence Design Professor of Electrical Engineering and Computer Science at Stanford University. Olukotun is well known as a pioneer in multicore processor design and the leader of the Stanford Hydra chip multipocessor (CMP) research project. Olukotun founded Afara Websystems to develop high-throughput, low-power multicore processors for server systems. The Afara multicore processor, called Niagara, was acquired by Sun Microsystems. Niagara derived processors now power all Oracle SPARC-based servers. Olukotun currently directs the Stanford Pervasive Parallelism Lab (PPL), which seeks to proliferate the use of heterogeneous parallelism in all application areas using Domain Specific Languages (DSLs). Olukotun is a member of the Data Analytics for What’s Next (DAWN) Lab which is developing infrastructure for usable machine learning. Olukotun is an ACM Fellow and IEEE Fellow for contributions to multiprocessors on a chip and multi-threaded processor design and is the recipient of the 2018 IEEE Harry H. Goode Memorial Award. Olukotun received his Ph.D. in Computer Engineering from The University of Michigan.




The slides of this seminar will not be posted online.





Introduction by chapter chair, Mojtaba Sharifzadeh.

Software 2.0 is Eating Software 1.0.

Software 2.0: Programming is Changing.

Microprocessor Trends.

Key Questions for Software 2.0.

Computational Models.

SGD: Statistical vs. Hardware Efficiency Trade-off.

Domain Specific Languages.

Next-Gen ML Accelerators.

Plasticine: A Reconfigurable Dataflow Architecture for Parallel Patterns.

Plasticine vs. FPGA (Stratix V)

Efficiency vs. Flexibility and Programmability.

Q&A with Audience.

Adjourn, IEEE Silicon Valley Committee and the Speaker…


Santa Clara Valley Chapter of the Solid State Circuits Society


September 2021

Next Meeting

“Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: a Pipelined ADC Example” – Prof. Jaeha Kim, Seoul National University (SNU)

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