Solid State Circuits Society

Febraury-21-2008

Our speaker was Kiran Gunnam, (LSI Corporation), and the topic of his presentation was  ” Area and Energy Efficient VLSI Architectures For Low-Density Parity-Check Decoders Using An On-The-Fly Computation“

Abstract

This talk* based on the speaker’s PhD research at Texas A&M University, presents several efficient decoder architectures for advanced error correction systems using low-density parity-check (LDPC) codes. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity and reduced memory requirements. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Several optimal and sub-optimal data flow graph and pipeline optimizations are provided for standard message passing decoding algorithm and layered decoding algorithm. Several key scheduling concepts such as block column processing, block serial processing, block parallel processing, out-of-order block processing for layered decoding, out-of-order layer processing, shuffled layered processing, multi-circulant processing, sub-parallelization are introduced for the LDPC decoder. The processor concepts such as value-reuse (based on Fossorier’s min-sum work in 1998), cache, speculative computation, dynamic state, multi-processor networks for reconfigurable permuters, partial bitonic sorter networks are applied in an efficient way for the decoder implementation.

Using this paradigm, the run-time configurable and multi-rate VLSI architectures for regular and irregular block LDPC codes are designed. Irregular block LDPC codes are specified for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. Regular block LDPC codes are specified for IEEE 802.3. Various other commercial applications that use block LDPC are DVB-S2, magnetic recording channel, holographic storage, DSL, etc. The proposed concepts are already incorporated/or being incorporated in several commercial designs.
Biography

Kiran Gunnam is currently a Principal ASIC Development Design Engineer in the storage product group at LSI Corporation. He received the MSEE and PhD in Computer Engineering from Texas A&M University . He has eight years of extensive research and development work experience in real time implementation of communication and signal processing systems on VLSI and programmable platforms (ASIC/FPGA/DSP). He previously worked at Marvell Semiconductor, Starvision Technologies, Schlumberger, Intel and Texas Engineering Experiment Station. His PhD research contributed several key innovations in advanced error correction systems based on LDPC. In addition his research and development work resulted in low complexity designs for several communication and signal processing applications such as signal processing design for a novel high precision navigation sensor called Visnav that is used for unmanned aerial refueling. Dr. Gunnam has 6 USpatent applications. He was elected as IEEE Senior Member in April 2007 for his significant contributions in integrated circuit design for signal processing and communication systems.

*This talk* is a condensed version of the speaker’s PhD defense public presentation given on Oct 11 2006 at Texas A&M University, and on October 3rd weeks and October 4th weeks of 2006 at Asilomar 2006 conference presentation, Marvell Semiconductor (Santa Clara) and Texas Instruments (Dallas). Parts of the speaker’s PhD presentation was also given in the following international conferences: January 2007:  VLSI Conference, Febraury 2007, ISWPC Conference, May 2007:  ISCAS Conference, June 2007:  ICC  Conference. For  more information on speaker’s research, please see http://www.linkedin.com/in/kirangunnam

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