Solid State Circuits Society

April 19, 2007

Our speaker was Mr. Sandeep Gupta, M.S.E.E., B.S.E.E. (Teranetics), and the topic of his presentation was ” Architectures and circuits for high speed, high accuracy time interleaved ADC’s. ”

Abstract
Time interleaved ADC’s are presented as efficient architectures to achieve high speed for a given accuracy of analog to digital converters. Impairments of time interleaved architectures and their impact on the choice of different architectures for high speed and high accuracy are discussed. Front End sampling circuits and sub-sampled ADC architectures suitable for different applications requiring 6-11bit resolution and 500MHz-15GHz speed are presented. Measured results are discussed for one of these ADC architectures for an application targeting 1GS/s 55dB SNDR.

Biography
Sandeep Gupta serves as Vice President of Mixed Signal Engineering at Teranetics, a company he co-founded in July 2003, focusing on 10GBASE-T Ethernet PHY development. At Teranetics he has delivered a complex chip including 1GS/s 11bit ADCs and DACs, low phase noise PLL, and analog and digital filters for a successful 10GBaseT PHY product. Prior to Teranetics, he led the design of analog chips at companies like Broadcom, Level One Communications and SGS Thomson, from 1994 to 2003. Sandeep received his Bachelor’s and Master’s in Electrical Engineering from Indian Institute of Technology, Kanpur. He has more than 25 patents issued or pending in the area of analog circuits and systems. He is the author of several IEEE publications, has done several standard contributions and served as an editor to the PMA electrical section of IEEE 802.3an (10GBASE-T Ethernet standard)

Some photos from the event.

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