Feb. 16th., 2006

Our speaker was  Mr. Anand Dixit, M.S.E.E., B.T.E.E. (Ph.D.E.E. student), and the topic of his presentation was Implementation and Productization of a Fourth generation 1.8 GHz dual-core SPARC V9 microprocessor.

Abstract

This fourth-generation processor combines two enhanced third-generation cores using an advanced 90-nm dual-Vt, dual-gate-oxide technology. Hardware additions feature expanded caches and inclusion of a 2-MB Level-2 cache and a Level-3 tag. Layout was completely redrawn to optimize the design for manufacturability and performance in the latest technology. Special emphasis was placed on library development to improve automation and assist in custom design. The memory design methodologies were completely updated to make quality design simpler and more robust. The chip operates at 1.8 GHz while dissipating 90 W of power at 1.1 V. Due to the big die size and complexity, converting a microprocessor design into a successful product is always a challenge – especially at new technology nodes. Second part of the talk will focus on the productization issues.

Biography

Anand Dixit received the Bachelor of Technology degree from Indian Institute of Technology, Kanpur, India, and the M.S. degree from Carnegie Mellon University, Pittsburgh, PA, both in electrical engineering, in 1996 and 1998, respectively. He is currently working towards the Ph.D. degree in electrical engineering at Stanford University, Palo Alto, CA.

From 1998 to 2000 Anand Dixit was with National Semiconductor, Santa Clara, CA, where he worked on touch screen controllers, PLLs and other analog designs for the Information Appliances group. Since 2000 he has been with Sun Microsystems, Inc., Sunnyvale, CA where he is responsible for the I/O designs on UltraSparc III and UltraSparc IV processors. His current interests include high-speed interface design, modern integrated circuit processing and processor test/debug. He holds a US patent on PLL lock detector.

Mr. Dixit was a recipient of the National Talent Search Scholarship from the Government of India between 1990 and 1996.

Welcome

Santa Clara Valley Chapter of the Solid State Circuits Society

Calendar

July 2025
M T W T F S S
 123456
78910111213
14151617181920
21222324252627
28293031  

Next Meeting

TBD

Search Previous Events