Silicon Valley Area Chapter


Heterogeneous Integration Roadmap: 3rd Annual Meeting 🗓 🗺

-- future of mobile, HPC, automotive, 5G, health, Chiplets, work on 2020 Roadmap ...

Dates: Thursday, February 20, 2020 (8:30 AM – 6:00 PM) and Friday, February 21, 2020 (8:30 AM – 4:00 PM)
Cost: $70 General Admission; $60 IEEE/ASME members and employees of SEMI member companies; $35 for retired, unemployed; free for full-time students. includes 2 lunches, wine-tasting
Location: SEMI World Headquarters, 673 South Milpitas Blvd, Milpitas CA USA
Information and Reservations:

NOTE: No photographs or videos are allowed during the Symposium. (This announcement complies with IEEE policies.)
Program Outline: (details below)
Day 1: From the 2019 Roadmap to HIR 2020
— Plenary Speakers from Intel and Google, with views of the future
— Moderated Sessions on the Released Roadmap and what comes next
— California Wine tasting
Day 2: TWG Working Group Workshop for HIR 2020
— Special Forum on the Rise of Chiplets
— Working Group breakout Sessions for HIR 2020
— Cross-Working Group Collaboration meetings

Roadmap Sponsors:

Summary: We are entering the era of the digital economy and ubiquitous connectivity with data migration to the cloud, smart devices everywhere, the Internet of Everything, and the emergence of autonomous vehicles. Artificial Intelligence and big data analytics are undergirding all market segments.
As we approach the inflection point of explosive expansion of innovations and electronic products into our global society, and the plateauing of CMOS’s scaling advantage, continued progress now requires a different phase of electronics innovation. Heterogeneous Integration is and will be the key technology direction going forward. It is the “low hanging fruit” for initiating a new era of technological and scientific advances to continue and complement the progression of Moore’s Law scaling into the distant future.
The Heterogeneous Integration Roadmap (HIR) published in 2019 is critically needed to focus on new materials and new devices, new architecture, designs, manufacturing processes and new methodologies to bring diverse components together into a System-in-Package (SiP). This is a pre-competitive technology roadmap addressing this future vision, difficult challenges, and potential solutions serving the industry, academia, government labs and research institutes and our professional careers.
Heterogeneous Integration requires a diverse set of disciplines and addresses a broad spectrum of applications. We have released this new Roadmap — a broad and inclusive worldview that comprehends this diversity, developed by a group of leading technical experts. It was made available in 2019 for integration into the planning cycles of companies, institutions, and government agencies around the world. The Roadmap is freely available to all potential users at no cost.

Program Agenda (subject to some adjustments)
Thursday, Feb 20, 2020: Implementation of HIR v1.0; Work on v2.0
Who should attend: Engineers and managers in the materials, device, packaging, supply chain, assembly and test disciplines; Open to the General Public
8:30: Registration and refreshments
9:00 – 9:10: Start of Program; Welcome by Ajit Manocha, SEMI CEO, and Nicky Lu, Etron Chairman
9:10: HIR Symposium Objective
9:25 – 9:55: Plenary Speaker: Virtuous Cycle of AI, Dr Pradeep Dubey, Intel Senior Fellow & Director, Intel Parallel Computing Lab
10:05 – 11:05: Session 1 – Heterogeneous Integration for Communications, Chair: Amr Helmy, Univ of Toronto & IEEE Photonics Society
— 5G, RF and Analog Mixed Signal: Tim Lee (Boeing), Herbert Bennett (Alta Tech)
— Mobile: William Chen (ASE), Benson Chan (Binghamton University)
— Aerospace & Defense: Tim Lee (Boeing), Jeff Demmin (Keysight)
— WLP (Fan-in & Fan-Out): Rozalia Beica (iNEMI), John Hunt (ASE)
— Simulation: Chris Bailey (University of Greenwich), Xuejun Fan (Lamar University)
— Materials & Emerging Research Materials: Bill Bottoms (3MTS)
11:05 – 11:15: Q&A
11:30 – 12:20: Session 2 – Heterogeneous Integration for Consumer & Industrial Applications, Chair: Ravi Mahajan, ASME EPPD & Intel
— Medical, Health & Wearables: Mark Poliks (Binghamton U), Nancy Stoffel (GE)
— SiP & Module: Rolf Aschenbrenner (Fraunhofer IZM), Klaus Pressel (Infineon), Erik Jung (IZM)
— Single Chip and Multi Chip Integration: William Chen (ASE), Annette Teng (Promex)
— Emerging Research Devices: Meyya Meyyappan (NASA Ames)
— Co-Design: Jose Schutt-Aine (University of Illinois)
12:20 – 12:30: Q&A
12:30 – 12:35: Thanks to Organizers and Patrons
12:35 – 1:30: LUNCH   (box lunch) and discussion time
1:30 – 2:00: Plenary Speaker: Dr. Hong Liu, The Role of Optics in Compute Infrastructure, Distinguished Engineer & Senior Director, Google Technical Infrastructure
2:00 – 2:50: Session 3 – Heterogeneous Integration for High-Performance Computing, Chair: Bill Bottoms, IEEE EPS & 3MTS
— High Performance Computing & Data Centers: Kanad Ghose (Binghamton University), Dale Becker (IBM), Rockwell Hsu (Cisco)
— 2D-3D & Interconnect: Ravi Mahajan (Intel), Subramanian Iyer (UCLA)
— Thermal Management: Madhusudan Iyenger (Google), Azmat Malik (Acuventures)
— Integrated Photonics: Amr Helmy (University of Toronto), Bill Bottoms (3MTS)
— Test: David Armstrong (Adventest)
2:50 – 3:00: Q&A
3:15 – 4:15: Session 4 – Heterogeneous Integration for Special Applications, Chair: Tom Salmon, SEMI
— Automotive: Urmi Ray (iNEMI), Rich Rice (ASE)
— MEMS & Sensor Integration: Shafi Saiyed (ADI)
— Integrated Power Packaging: Patrick McCluskey (U-Md), Doug Hopkins (NCSU)
— Cyber Security: Sohrab Aftabjahani (Intel)
— Supply Chain: Paul Trio (SEMI)
— IoT: Robert Lo (ITRI)
4:15 – 4:25: Q&A
4:25 – 5:20: HIR Open Forum: Feedback & Comments
5:20 – 5:35: Next-Day TWG Workshop Preparation
Symposium Closing
5:45 – 6:45: California Wine Tasting

Friday, Feb 21, 2020: HIR Technical Working Group Workshop
(All are invited to associate with one of the TWGs and participate in its analysis and deliberations; lunch is included)
8:30 – 9:00: Registration and coffee at SEMI Hdqtrs, Milpitas
9:00 – 9:20: All-HIR TWG Overview; HIR 2020 Revision Preparation
9:20 – 10:00: “The Rise of Chiplets” Special Forum
— Invited Speakers: David Kehlet (Intel), Babi Vinnakota (ODSA)
10:00 – 11:30: TWG Breakout Workshop I
11:30 – 12:00: All-TWG Breakout Session Report
12:00: Lunch (box lunches provided)
1:00 – 1:30: Planning for ECTC HIR Workshop & 2020 HIR Events
1:30 – 3:00: TWG Breakout Workshop II
3:00 – 3:30: All-TWG Breakout Session Report
3:30 – 4:00: Closing Remarks and Wrap-Up
4:00 – 5:30: Space available for TWG informal discussions and Cross-TWG collaborations (optional)

Hosted by SEMI   SEMI 
(The first day had been planned for Samsung Foundry; however, due to an abundance of caution relating to staff and visitor health, Samsung has decided to limit large events on their San Jose campus. Our thanks to Samsung for their willingness to host.)
Health Alerts:
— please do not attend if you have been in China (excludes Taiwan) in the last 15 days. We will refund.
— please do not attend if you are not feeling well. We will refund.
— We are expecting a full house and are taking precautions to keep us all healthy. Avoid handshakes (try a fist-bump or short bow). Hand sanitizers will be provided. Microphones will be sterilized.

We thank our Annual Meeting supporters for 2020:
        GOOGLE     Cisco Silitronics
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Samsung Auditorium, San Jose Map