Speakers: several short tech updates; then John H Lau, Unimicron Technology Corporation

Meeting Date: Thursday, March 26, 2026
Location: SEMI Headquarters, Milpitas
Time: 11:30 AM for sandwiches, drinks, and networking; Presentations begin at 12:00 noon (PST), ending at 1:30 PM
Cost: $10 (no charge for EPS members, and for IEEE members will join EPS this spring — half price)
Reservations: events.vtools.ieee.org/m/539468
Program: Several 5-minute tech updates (hybrid bonding; HI Roadmap); How to upgrade to Senior Member.
Keynote Talk Summary: Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) such as the photodiode laser, etc. and the electrical engine (EE) which consists of the electronic ICs (EIC) such as the laser driver, transimpedance amplifier, etc. as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of switch, PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture:
— Silicon Photonics
— Data Centers
— Optical Transceivers
— Optical Engine (OE) and Electrical Engine (EE)
— OBO (on-board optics)
— NPO (near-board optics)
— CPO (co-packaged optics)
— 3D Integration of the PIC and EIC
— 3D Heterogeneous Integration of PIC and EIC
— 3D Heterogeneous Integration of ASIC Switch, PIC and EIC
— 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges
— 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate
— Various Forms of CPO

Bio: John Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 540 peer-reviewed papers (390 are the principal investigator), 54 issued and pending US patents (35 are the principal inventor), and 25 textbooks. John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.