Organized by the IEEE-SCV CAS Chapter
Speaker: Prof. Subhasish Mitra, Dept. of EE and Dept. of CS, Stanford University

Meeting Date: Thursday, April 21, 2022 (was March 24)
Time: Checkin via WebEx at 5:50 PM; Presentation at 6:00 PM (PDT)
Cost: none
Reservations: www.eventbrite.com
Summary: The computation demands of 21st-century abundant-data workloads, such as AI/machine learning, far exceed the capabilities of today’s computing systems. For example, a Dream AI Chip would ideally co-locate all memory and compute on a single chip, quickly accessible at low energy. The next leap in computing performance requires the next leap in integration, to seamlessly fuse disparate parts of a system — e.g., compute, memory, inter-chip connections — synergistically for large energy and execution-time benefits.
This talk presents transformative NanoSystems by exploiting the unique characteristics of emerging nanotechnologies and abundant-data workloads. We create new chip architectures through ultra-dense (e.g., monolithic) 3D integration of logic and memory – the N3XT 3D approach. Multiple N3XT 3D chips are integrated through a continuum of chip stacking/interposer/wafer-level integration — the N3XT 3D MOSAIC. To scale with growing problem sizes, new Illusion systems orchestrate workload execution on N3XT 3D MOSAIC, creating an illusion of a Dream Chip with near-Dream energy and throughput. Beyond existing cloud-based training, we demonstrate the first non-volatile chips for accurate edge AI training (and inference) through new incremental training algorithms that are aware of underlying non-volatile memory technology constraints.
Several hardware prototypes demonstrate the effectiveness of our approach. We target 1,000X system-level energy-delay-product benefits, especially for abundant-data workloads. Such large benefits enable coming generations of applications that push new frontiers, from deeply-embedded computing systems all the way to the cloud.
Bio: Subhasish Mitra is Professor of Electrical Engineering and Computer Science at Stanford University. He directs the Stanford Robust Systems Group, leads the Computation Focus Area of the Stanford SystemX Alliance, and is a member of the Wu Tsai Neurosciences Institute. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Results from his research group have influenced almost every contemporary electronics system, and have inspired significant government and research initiatives in multiple countries. He has held several international academic appointments — the Carnot Chair of Excellence in NanoSystems at CEA-LETI in France, Invited Professor at EPFL in Switzerland, and Visiting Professor at the University of Tokyo in Japan. Prof. Mitra also has consulted for major technology companies including Cisco, Google, Intel, Samsung, and Xilinx.