Speaker: Zia Karim, PhD, Chief Technology Officer (CTO), Yield Engineering Systems
Meeting Date: Thursday, May 6, 2021
Time: Checkin via WebEx at 11:50 AM; Presentation at 12:00 noon (PDT)
Summary: Advances in IC backend processing are rapidly extending the capabilities of heterogeneous and 3D integration. Both high-bandwidth memory (HBM) and dynamic random-access memory (DRAM) have already benefited from considerable progress in 3D integration fueled by 3D stacking of memory. By enabling the stacking of a variety of chiplets and other components, 3D system integration can deliver high compute density and high performance at low cost. However, although dissimilar chips can be connected on organic, glass, silicon or fan-out substrates using multi-layer RDLs (redistribution layers), many of these complex products now have an effective temperature limit of 250°C because of the need to transition to copper interconnect as well as to manage fan-out stress. This new requirement to limit overall thermal budget has given rise to a challenge for Polyimide (PI), Photo Imageable Dielectric (PID), and Photo Sensitive Polyimide (PSPI) process technology, which must now enable a faster cure at lower temperatures while also delivering better film properties.
This talk will summarize research done on the physical, mechanical, thermal, and electrical properties of various types of Polyimide and Poly-Benz-Oxazole (PBO) materials after curing under different process parameters, under atmospheric and vacuum process conditions. At both conventional and low temperatures, the vacuum process resulted in higher thermal stability, lower outgassing, and better thermal properties. The vacuum cure also showed better dielectric strength as well as lower dissipation factor. The assumption that curing under vacuum reduces the amount of volatile and volatilizable material remaining in the film appears to be consistent with these results.
Based on this study, the multi-level metallization process of Fan Out Wafer Level Packaging (FOWLP) and Fan Out Panel Level Packaging (FOPLP) would seem to benefit from the use of sub-atmospheric curing or annealing technology at low temperature, given the demonstrated improvements in both the quality and the performance of the cured polyimide films. This conclusion has relevance for RDL applications and, consequently, for 3D stack integration.
Bio: Zia Karim, an IEEE Sr. Member, is currently Sr. Vice President and Chief Technology Officer (CTO) at YES (Yield Engineering Systems, Inc.), a leading supplier of semiconductor equipment for backend Advanced Packaging processes. Dr. Karim was previously Vice President of Business Development and Technology at AIXTRON/Genus (acquisitions) where he worked for over 15 years. Dr. Karim also held senior management positions at Applied Materials and Novellus, after starting his career at Sharp Microelectronics in 1994.
Dr. Karim received his PhD in Electronic Engineering from Dublin City University in Ireland, and his B.Sc. and M.Sc. degrees in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology. He recently completed the Certificate of Business Excellence in Executive Education from UC Berkeley’s Haas School of Business.
A pioneer in positioning W/WSi CVD, Low K PECVD, High K ALD, and III-V MOCVD processes for semiconductor logic and memory devices, Dr. Karim organized and moderated “III-V on Si” seminars jointly with Sematech at every pre-IEDM between 2006 and 2012. In addition to organizing or co-organizing several conference symposia and related transactions — including IWLPC, ECS and AVS — Dr. Karim has authored more than 40 published papers in peer-reviewed journals and holds 17 patents.