Energy-Efficient RISC-V Processors in 28nm FDSOI
Energy-Efficient RISC-V Processors in 28nm FDSOI
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Date: Tuesday, November 14th, 2017 Speaker: Prof. Borivoje Nikolic Time: 6:30 PM (PT) Networking/Refreshments, Location: Cadence / Bldg 10, |
Abstract
This talk presents the design of a series of energy-efficient microprocessors done by a group of students at UC Berkeley. They are based on an open and free Berkeley RISC-V architecture and implement several techniques for operation in a very wide voltage range utilizing 28nm FDSOI. To enable agile dynamic voltage and frequency scaling, with high energy efficiency the designs feature an integrated switched-capacitor DC-DC converter and direct power measurement, with an integrated power-management unit. A custom-designed SRAM-based cache operates in a wide 0.45-1V supply range. Techniques that enable low-voltage SRAM operation include 8T cells, assist techniques and differential read.
Speaker Bio
Borivoje Nikolić is the National Semiconductor Distinguished Professor of Engineering at the University of California, Berkeley. He received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999. His research activities include digital, analog and RF integrated circuit design and communications and signal processing systems. He is co-author of the book Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall, 2003. Dr. Nikolić received many awards in his career, including the NSF CAREER award in 2003, and the best paper awards at the IEEE International Solid- State Circuits Conference, Symposium on VLSI Circuits, IEEE International SOI Conference, European Solid-State Circuits Research Conference, European Solid-State Device Research Conference, S3S conference and the ACM/IEEE International Symposium of Low- Power Electronics.
Note : The doors close at 7:30 PM