Top SoC Design Challenges – Panel

Date: Tuesday, April 8, 2014, 6:30 PM
Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, CA (map)
Naresh Sehgal, Intel, SW Director for FPGA based Silicon platforms for Mobile products
Paul McLellan, SemiWiki Project, Blogger & EDA Expert
Tom Dillinger, Oracle, CAD Technology
John Swan, Swan on Chips, SoC Technologist


Time: 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation

Registration: Please register by ordering a ticket below


This talk features a panel of leading experts discussing the top challenges of SoC design in today’s competititve world. Hans Spanjaart will be the moderator for the discussions.


Hans Spanjaart Bio


Hans Spanjaart is Sr. Program Manager of Altera’s SoC FPGA product line. He has over 25 years of experience in the semiconductor industry, leading engineering teams in a range of research and development programs, including embedded processors, media processors, complex SoCs, compilers, software and mixed-signal.


Naresh Sehgal Abstract

Semiconductor Design process, as challenging as it has become, is still only half the story as the other half is to validate the product before sending it to market. Current validation techniques and processes will be discussed, and areas where some changes are needed shall be called out.

Download position statement here

Naresh Sehgal Bio


Naresh is a SW Manager at Intel Corp, responsible for new architectural investigations. He has been with Intel for 22 years in various roles, including EDA development, Silicon Design Automation, Intel-HP Alliance management and for launching Virtualization technology on all Intel platforms. Naresh holds a PhD in Computer Engineering from Syracuse Univ, and MBA from Santa Clara Univ. He holds 4 patents and authored more than 20 publications in the CAD domain.


Paul McLellan Abstract

A year ago everyone assumed that the future of semiconductor fabrication below 28nm was going to be primarily FinFET, with the exception of ST who put all their eggs in the FD-SOI basket. But increasingly FD-SOI is looking more attractive for everything except the highest performance designs. It is easier to migrate designs and IP, easier to do analog design (no quantization of transistor sizes), low power, cheap to manufacture. What’s not to like?

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Paul McLellan Bio


Paul McLellan has a 30 year background in semiconductor and EDA with both deep technical knowledge and extensive business experience. He works as a consultant in EDA, embedded systems and semiconductor. Paul was educated in Britain and spent the early part of his career as a software engineer at VLSI Technology both in California and France, eventually becoming CEO of Compass Design Automation. Since then he was VP engineering at Ambit, corporate VP at Cadence, VPs of marketing at VaST Systems Technology and Virtutech, and CEO at Envis Corporation. He blogs at and has published a book EDAgrafitti on the EDA and semiconductor industries.


Tom Dillinger Abstract

With apologies to David Letterman, we’ll highlight the leading technical challenges that chip designers are currently facing, and the corresponding CAD algorithm and tool development initiatives underway to address them. Many of these issues have been around for a while, but have become more intricate to manage, with the increasing complexity of current fabrication processes. However, there is one challenge ahead that will disrupt traditional design flows substantially — the traditional design role will forever be transformed.

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Tom Dillenger Bio


Tom Dillinger works for the Microelectronics Division of Oracle Corporation, on the tools and technologies for the design of SPARC microprocessors and chipsets. Previously, he has worked on processor and SoC design methodology for IBM, Conexant, and AMD. He is the author of the text, VLSI Engineering, by Prentice-Hall.


John Swan Abstract

The design flow is broke, but you didn’t know it! The common answer to improve the design flow is to add more resources at verification, and doing that at RTL . If we do a Shift Left into earlier verification & validation, at ESL, we can not only accomplish earlier functional confidence, but we can now do design refinement which includes HW/SW architectural exploration for higher performance and lower power. John will also review program for the Electronic Design Process Symposium (EDPS) occurring the week following this panel session.

Download position statement here

John Swan Bio


John worked on IC design and design methodology for 20 years at Motorola Labs covering the design flow from requirements and HDL entry through layout. John also worked as an SoC Consulting Manager and as IP Product Marketing Manager. John is now on contract with EDATechForce to insert leading-edge SoC & FPGA design technology into design teams. John was Awarded the IEEE Computer Society’s Golden Core and Meritorious Service Awards in 2012 for his leadership role as Chair of the CS Chapter of Silicon Valley. John earned a BSEE degree with High Honors in Computer Engineering at the Illinois Institute of Technology. He has an MBA from Roosevelt University.

Stream Presentation [Requires MS Silverlight]

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