Electronic Design Process Symposium

23rd Annual

Electronic Design Process Symposium
Cyber Security Workshop

April 21 & 22, 2016

Monterey Tides Hotel, Monterey, CA

The Electronic Design Processes Symposium (EDPS) provides a forum for a cross-section of the top thinkers, movers, and shakers who focus on how chips and systems are designed, and to discuss state-of-the-art electronic design processes and CAD methodologies. The symposium focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.

www.ieee-edps.org – program & registration

Promo code – $50 Off – CSatEDPS

Sponsored by:


CS Chapter of Silicon Valley



2016 Keynote Speakers
Ken Caviasca VP, R&D, Intel
Serge Leef VP, Mentor Graphics
Cmdr. Chris Eagle Sr. Lecturer, Naval Post Graduate School

Thursday 4/21 Session Themes:

  • FPGA Prototyping IOT Designs (panel)
  • Low Power Design Methodology (panel)
  • Multi-Die IC Design & Applications (panel)

 Friday 4/22 Cyber Security Workshops (by Riscure)

  • Side Channel Analysis (SCA) Workshop
  • Fault Injection (FI) Workshop

Full buffet breakfast both days!