Sponsor: San Diego Section
Speaker: Dr. Timothy M. Hollis

Meeting Date: May 6, 2021
Time: 11AM
Cost:
Reservations: IEEE

Summary:
Several factors drive the demand for DRAM bandwidth scaling: in addition to established applications in visualization, there has been a proliferation of data-intensive applications enabled by advancements in AI, ML and advanced driver-assistance systems (ADAS) [1]. While high-bandwidth memory (HBM) provides an alternative solution, its high cost makes it impractical for many applications. On the other hand, extending the GDDR roadmap beyond GDDR6 through per-pin bandwidth scaling presents significant obstacles: including the reduced link-timing budget and the slow DRAM transistors. This paper introduces an 8Gb DRAM with a single-ended PAM4 interface to redirect and extend the GDDR roadmap. The design supports 22Gb/s/pin in a conventional 1Ynm DRAM process.

Bio: Dr. Timothy M. Hollis was born in Palo Alto, CA. He received the B.S. degree in Electrical Engineering from the University of Utah, Salt Lake City, UT in 2003 and the Ph.D. degree in Electrical Engineering from Brigham Young University, Provo, UT in 2007.

He joined the DRAM organization of Micron Technology, Inc., Boise, ID, in 2006 as a circuit designer in the Advanced Architecture group. From 2012-2014 he was a Chipset Architect at Qualcomm, San Diego, CA. He returned to Micron in 2014 where, as a Micron Fellow, he presently leads a Memory Interface Pathfinding team. He has published 17 articles in journals, conference proceedings and technical magazines and holds 163 issued US and international patents.