Solid State Circuits Society

Electrical Signaling at 64Gb/s/Lane

Electrical Signaling at 64Gb/s/Lane

Speaker: Dr. Elad Alon, UC Berkeley

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Abstract:

The demand for I/O bandwidth in modern SoCs continues to grow at an exponential rate, forcing the per-lane bandwidth of electrical links to rise at a tremendous pace.  While there have been several demonstrations of electrical I/O operating at ~40Gb/s/lane to date, achieving these data-rates has so far come at the cost of substantial penalty in energy-efficiency vs. optimized lower-rate designs.

In this talk, I will describe our on-going work in pushing the data-rate of electrical links to 64Gb/s and beyond.  I will begin by describing a proposed active connector topology as well as the methodology we used to elucidate the feasibility of links operating at this rate over ~1m of cable interconnect.  I will next move on to describe our first experimental demonstration of a critical component within such a link – specifically, a multi-tap decision feedback equalizer.  Through a series of design optimizations that I will describe in the talk, this closed-loop, 3-tap design achieves 66Gb/s error-free operation over 1e13 bits with only 46mW of power consumption in a standard 65nm CMOS process.

Bio: 

Elad Alon received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from StanfordUniversity in 2001, 2002, and 2006, respectively. In Jan. 2007, he joined the University of California at Berkeley, where he is now an Associate Professor of Electrical Engineering and Computer Sciences as well as a co-director of the Berkeley Wireless Research Center (BWRC). He has held consulting or visiting positions at a number of leading semiconductor companies, where he worked on digital, analog, and mixed-signal integrated circuits for computing, test and measurement, and high-speed communications. Dr. Alon received the IBM Faculty Award in 2008, the 2009 Hellman Family Faculty Fund Award as well as the 2010 UC Berkeley Electrical Engineering Outstanding Teaching Award, and has co-authored papers that received the 2010 ISSCC Jack Raper Award for Outstanding Technology Directions Paper, the 2011 Symposium on VLSI Circuits Best Student Paper Award, and the 2012 Custom Integrated Circuits Conference Best Student Paper Award. His research focuses on energy-efficient integrated systems, including the circuit, device, communications, and optimization techniques used to design them.

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