Technical Talks on High Speed ADCs

High Speed ADC’s (Flash, Time interleaved pipeline)

Speaker: Shwetabh Verma, Broadcom Corp. /Brian Setterberg, Agilent Technologies

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First Talk:  A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications

by Shwetabh Verma, Broadcom Corporation

Abstract: A 40-nm CMOS 10-GS/s, 6-bit Flash ADC has been designed for a DSP-based receiver which meets the requirements for all NRZ 10G Ethernet standards. The ADC uses both conventional comparator calibration and redundancy to reduce power. The micro-architecture enables dynamic reconfiguration of the comparator order – reducing the required comparator offset adjustment range during ADC calibration. The ADC occupies 0.27mm2 and consumes 240mW.

Bio: Shwetabh Verma received the BS degree from the University of Toronto in 1998, and the MS and PhD degrees from Stanford University in 2000 and 2005 respectively. His graduate work focused on the design of low-cost, low-power technology for wireless personal area networks. Since 2005 he has been employed at Aeluros Inc., now part of Broadcom, designing circuits and systems for broadband data communications.

Second Talk: A 14b 2.5GS/s 8-Way Interleaved Pipelined ADC With Background Calibration and Digital Dynamic Linearity Correction
by Brian Setterberg, Agilent Technologies

Abstract: Eight 14 bit pipelined ADCs are time interleaved to provide an aggregate 2.5 GS/s conversion rate. The interleaved architecture enables a metastable error rate below 1E-17 to meet the stringent requirements of test and measurement applications. Continuous background calibration and digital dynamic linearity correction enable the interleaved architecture to achieve 78 dB SFDR over a signal bandwidth of more than 1 GHz.

Bio: Brian Setterberg holds a Bachelor of Science degree in electrical engineering from Washington State University and a Master of Science degree in electrical engineering from Stanford University. He joined Hewlett Packard Laboratories in 1997 to develop mixed-signal integrated circuits for radio applications. He is currently with Agilent Research Laboratories, where his recent work has been focused on high performance analog to digital converters optimized for test and measurement systems.

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Santa Clara Valley Chapter of the Solid State Circuits Society

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