IEEE Santa Clara Valley Chapter
High-Speed Wireline Tranceivers
High-Speed Wireline Transceivers
Speaker: Dr. Jafar Savoj from Xilinx Corporation
Venue:
Texas Instruments Building E Auditorium, 2900 Semiconductor dr., Santa Clara, CA 95051
Time: March 13th (Thursday) evening 6.30 pm-8.30pm.
Networking and snacks : 6.30 PM- 7:00 PM
Technical Talk : 7.00 PM- 8.00 PM
Abstract:
This presentation describes the design of fully-adaptive multi-standard wireline transceivers targeted for high-speed communication over a wide range of channels. Architectural solutions resolving channel-induced signal distortion along with adaptation techniques for reliable operation across PVT are introduced. Clocking circuit techniques for wide-range operation using ring and LC PLLs as well as injection locked PLLs are proposed. Finally, implementation of these techniques in multiple fully-adaptive transceivers in 28nm CMOS is demonstrated.
Bio:
Jafar Savoj received the B.Sc. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1996, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles, in 1998 and 2001, respectively.
He is currently a Senior Engineering Director with the Serdes Technology Group at Xilinx, San Jose, CA, and leads high-speed, low-power wireline transceiver development for FPGA applications. He serves as a technical program committee member of ISSCC (Analog Subcommittee). Previously, he served as a technical program committee member of the IEEE CICC and the IEEE Symposium on VLSI Circuits, and a guest editor and an associate editor for the IEEE Journal of Solid-State Circuits.
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