Solid State Circuits Society

Despite increasing economic and technical challenges to scale CMOS, we continue to witness unprecedented performance with 22-nm fully-depleted tri-gate devices now in production.  This tutorial offers a summary of how CMOS device technology has progressed over the past two decades.  We will review MOS device and short-channel fundamentals to motivate how device architectures in production have evolved to incorporate elements such as halos and spacers, mechanical strain engineering, high-K dielectric and metal gate, and fully-depleted fins.  We will also examine key process technologies that have enabled the fabrication of these devices.

Biography:

Alvin Loke (S’89-M’99-SM’04) received the BASc (Eng. Physics) degree with highest honors from the University of British Columbia in 1992, and the MSEE and PhDEE degrees from Stanford University in 1994 and 1999 respectively.  He was recipient of the UBC Chancellor Entrance and Canadian NSERC 1967 Graduate Scholarships.  While at Stanford, his research focused on copper interconnects with low-K polymer dielectric.  He has interned at Texas Instruments, Motorola, and at Sumitomo Electric Industries.  From 1998 to 2001, he worked on CMOS technology integration at HP Labs, Palo Alto, CA and then at Chartered Semiconductor Manufacturing, Singapore as an Agilent assignee.  In 2001, he transferred to Fort Collins, CO, where he designed CMOS phase-locked loop circuits for low-jitter embedded SerDes I/O and ASIC core clocking.

In 2006, he joined Advanced Micro Devices where he is currently a Principal Member of Technical Staff designing high-speed links and addressing analog/mixed-signal concerns for next generation CMOS.  Dr. Loke has authored 38 publications and holds 12 US patents.  He presently serves on the CICC technical program committee, SSCS Chapters committee, and ECE Department Industrial Advisory Board at Colorado State University. He is presently the SSCS Webinar Taskforce Chair, a Guest Editor for the IEEE Journal of Solid-State Circuits, and a SSCS Distinguished Lecturer.

Texas Instruments Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map.  Refreshments are provided at 6:00 PM and the talk typically begins at 6:30 PM.Donations requested to partially cover food cost.The talks are open to everyone, feel free to join us even if you are not an IEEE member yet.