Solid State Circuits Society

We investigate state-of-the art technology that accelerates analog design by automatically custom sizing an architecture to satisfy specifications for a chosen process over process, voltage and temperature (PVT) variations.  The talk begins with an overview of manual and automated circuit design methods and identifies the iterative and time-intensive steps that result in the analog bottleneck.  We then describe how an equation-based optimizer and optimization friendly process-models are combined with a unified system and circuit formulation that is independent of specification and process to enable analog/RF circuits to be designed and ported efficiently while also documenting the operation of the circuit.  Then, innovations and ease-of-use features that address difficulties associated with traditional equation based optimization methods are presented.  The talk concludes with illustrative applications of commercial equation-based optimization tools in ADC, PLL, RF LCO, opamp, regulator and Serdes designs to highlight how this compelling methodology is leveraged for  process and corner aware, simultaneous optimization of system and circuit across different levels of hierarchy and abstraction.

S. S. Mohan received the B.S., M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, where he focused on the design and optimization of CMOS analog and RF circuits.  He has twenty years experience in circuit design and automation and has designed GPS chips, medical electronics, Serdes RF LCOs and multi-phase VCOs, gigabit-ethernet front-ends and shunt-peaked amplifiers.  He served as Chief Scientist at Sabio Labs prior to its acquisition by Magma Design Automation where he became Senior Director in charge of the analog and mixed-signal circuit design group.  He has taught analog design classes at Stanford as a teaching assistant and visiting faculty and received the Centennial Award for Teaching.  Mohan currently leads the circuit team at Synopsys that creates reusable PLL, ADC, Serdes, RF LCO, Bandgap, Opamp and regulator FlexCells leveraging its proprietary optimizer (ADX).

SCV SSCS Technical meetings are typically held on The THIRD Thursday of each month at:

Texas Instruments Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map.  Refreshments are provided at 6:00 PM and the talk typically begins at 6:30 PM.Donations requested to partially cover food cost.The talks are open to everyone, feel free to join us even if you are not an IEEE member yet.