Solid State Circuits Society

Limited scaling of both on-chip and off-chip interconnects has led to energy-efficiency and bandwidth density constraints that are emerging fast as the major performance bottlenecks in embedded and high-performance digital systems. While optical interconnects have shown promise in extensive architectural studies to date significant challenges need to be overcome both in device and circuit design as well as the integration strategy. Pushing the photonic link energy efficiencies below sub-100 fJ/bt will require monolithic integration of silicon photonic interconnects within manycore processor die to minimize the energy spent on interconnect parasitics that are significant even between 3D-stacked dies.
In this lecture we describe experimental and modeling efforts in designing high-performance, energy-efficient, monolithically integrated photonic links. The link modeling illustrates the inherent trade-offs between circuit and device components and points both in directions of efficient system approaches and critical device design sensitivities. The experimental platform for monolithic integration of silicon photonic devices into a mainstream sub-100nm foundry CMOS process flow will also be described. This platform serves as an infrastructure hub for research in photonic device design, integration and process issues as well as circuit design. It facilitates full integration of circuits and photonic components and high-speed in-situ testing infrastructure.

Vladimir Stojanovic is the Emanuel E. Landsman Associate Professor of Electrical Engineering and Computer Science at MIT. His research interests include design, modeling and optimization of integrated systems, from CMOS-based VLSI blocks and interfaces to system design with emerging devices like NEM relays and silicon-photonics. He is also interested in design and implementation of energy-efficient electrical and optical networks, and digital communication techniques in high-speed interfaces and high-speed mixed-signal IC design. Vladimir received his Ph.D. in Electrical Engineering from Stanford University in 2005, and the Dipl. Ing. degree from the University of Belgrade, Serbia in 1998. He was also with Rambus, Inc., Los Altos, CA, from 2001 through 2004. He received the 2006 IBM Faculty Partnership Award, and the 2009 NSF CAREER Award as well as the 2008 ICCAD William J. McCalla, 2008 IEEE Transactions on Advanced Packaging, and 2010 ISSCC Jack Raper best paper awards. He is an IEEE Solid-State Circuits Society Distinguished Lecturer for the 2012-2013 term.

SCV SSCS Technical meetings are typically held on The THIRD Thursday of each month at:

Texas Instruments Building E Auditorium
2900 Semiconductor Dr., Santa Clara, CA 95051 Directions and Map.  Refreshments are provided at 6:00 PM and the talk typically begins at 6:30 PM.Donations requested to partially cover food cost.The talks are open to everyone, feel free to join us even if you are not an IEEE member yet.