Solid State Circuits Society

June 8, 2010

Speaker: Jason Howard Senior Technical Researcher, Intel

Title: 48-Core Cloud Computer Chip

Location: National Semiconductor, Building E Conference Center  2900 Semiconductor Drive

Date/Time: Jun 8th, 6:30 pm Networking with food and beverage 7:00 pm Presentation

Registration: Free – ($2 donation helps us cover food)

Abstract:

In this talk, Jason Howard describes a processor integrating 48 IA-32 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 6×4 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet switched router shared between two cores. Core-to-core communication uses message passing while exploiting 384KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1V, cores operate at 1GHz while the 2D-mesh operates at 2GHz. As performance and voltage scales, the processor dissipates between 25W and 125W. The 567mm^2 processor is implemented in 45nm Hi-K CMOS and has 1,300,000,000 transistors

Bio:

Jason Howard is a senior technical research lead for the Advanced Microprocessor Research team within Intel Labs, Hillsboro, Oregon. During his time with Intel Labs, Howard has worked on projects ranging from high performance low power digital building blocks to the 80-Tile TeraFLOPs NoC Processor. His research interests include alternative microprocessor architectures, energy efficient design techniques, variation aware and tolerant circuitry, and exascale computing. Jason Howard received the B.S. degree and M.S degree in electrical engineering Brigham Young University, Provo, UT, in 1998 and 2000 respectively. He joined Intel Corporation in 2000. He has authored and co-authored several papers and has several patents issued and pending.

Co-sponsored with IEEE SCV Computer Society

Welcome

Calendar

Next Meeting

Search Previous Events