Solid State Circuits Society

Oct 15 2009

Our speaker was Sefan Rusu (Intel Corporation), and the topic of his presentation was “Nehalem-EX: a 45nm, 8-core Enterprise Processor“

Abstract

This talk describes a 2.3B transistors, 8-cores, 16-threads 64-bit Xeon® EX processor with an on-die 24MB shared L3 cache. The processor is implemented in a 45nm, 9-metal high-K metal gate process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency. The point-to-point I/O links are operating at 6.4GT/s and achieve 25.6GB/s per port.

Biography

Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience includes over 18 years with Intel Corporation and 6 years at Sun Microsystems. He is presently a Senior Principal Engineer in Intel’s Enterprise Microprocessor Group leading the technology and special circuits design activities for the Xeon® EX Processors. He has authored over 80 papers on VLSI circuit technology and holds 33 U.S. patents. He is an IEEE Fellow, a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences and an Associate Editor of the IEEE Journal of Solid-State Circuits. He received the ISSCC 2009 Beatrice Winner Award for Editorial Excellence and is a Distinguished Lecturer of the Solid-State Circuits Society.

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