Solid State Circuits Society

May 21 2009

Our speaker was  Nikola Nedovic (Fujitsu Laboratories of America), and the topic of his presentation was  ” Clock and Data Recovery in High-Speed Wireline Communications”

Abstract

The presentation reviews the basics of clock and data recovery circuits in high speed transceivers for optical communications, with focus on top-down design strategy from practical standpoint. Covered topics include selection of loop parameters, limitations of the linear model, pull-in process and false lock, and effect of the circuit parameters on system performance. The second part of the presentation is dedicated to exploration of properties, design and laboratory measurement of hybrid oversampling CDR’s, intended to give an insight on the impact of architecture on the behavior of the CDR.

Biography

Nikola Nedovic is a member of research staff at Fujitsu Laboratories of America, Sunnyvale, CA. He received a Dipl.Ing. degree in electrical engineering from the University of Belgrade, Serbia, in 1998 and the Ph.D. degree from the University of California at Davis, in 2003. In 2001, he joined Fujitsu Laboratories of America, Inc., Sunnyvale, CA, where he works in the area of high-speed communications and high-performance and low-power VLSI circuits. His research interests include high-speed analog and mixed-signal circuits for wireline communications, clock and data recovery, and circuit design and clocking strategies for high-performance and low-power digital applications.

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