Solid State Circuits Society

February 12 2009

Our speaker was Hyunsik Park (Atheros), and the topic of his presentation was  ” High-Precision Low-Voltage Low-Power Analog-to-Digital Conversion”

Abstract

This presentation introduces a power-efficient, chopper-stabilized switched capacitor sigma-delta (ΣΔ) modulator that combines delayed input feedforward and single comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-µm CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870-µW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.

Biography

Hyunsik Park (S’03 M’09) was born in Daegu, Korea in 1976. He received the B.S. degree in electronic engineering from the Yonsei University, Seoul, Korea in 2001 and M.S. degree in electrical engineering from Stanford University, Stanford, CA, in 2003. He is currently working toward the Ph.D degree in electrical engineering at Stanford University, Stanford, CA. His doctoral research focuses on high-precision, low-voltage, low-power analog-to-digital conversion. He is currently with Atheros Communications, Santa Clara, CA as a Member of Technical Staff since October 2008. His research interests include the design of mixed-signal systems and RF circuits. He was the recipient of the 2008 Analog Devices Outstanding Student Designer Award.

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