IEEE Santa Clara Valley Chapter
August 21, 2008
Presenter: Stefan Rusu, Sr. Principal Engineer, Intel Corp., Santa Clara, CA Title: Power and leakage reduction in the nanoscale era
Abstract: To continue harvesting the technology scaling benefits, it is essential for chip designers to understand the nature and impact of active power and leakage, its sensitivity to different design parameters, and practical techniques to reduce it. This talk will review design techniques for active power and leakage management with examples from recent industry designs and academic research.
Biography: Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience ncludes over 15 years with Intel Corporation and 6 years at Sun Microsystems. He is presently a Senior Principal Engineer in Intel’s Enterprise Microprocessor Group leading the technology and special circuits design activities for the Xeon® MP Processors. He has authored over 75 papers on VLSI circuit technology and holds 30 U.S. patents. He is an IEEE Fellow, a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences and an Associate Editor of the IEEE Journal of Solid-State Circuits.
| M | T | W | T | F | S | S |
|---|---|---|---|---|---|---|
| 1 | 2 | |||||
| 3 | 4 | 5 | 6 | 7 | 8 | 9 |
| 10 | 11 | 12 | 13 | 14 | 15 | 16 |
| 17 | 18 | 19 | 20 | 21 | 22 | 23 |
| 24 | 25 | 26 | 27 | 28 | 29 | 30 |