IEEE Santa Clara Valley Chapter
September 20, 2007
Our speaker was Mr. Umesh Nawathe (Senior Manager of Sun Microsystems), and the topic of his presentation was “Physical Design of SUN Niagara2 Processor. “
Abstract
Niagara2 is the 1st 64-bit 64-thread SPARC ‘System on a chip’ from SUN based on the power-efficient CMT architecture optimized for Space, Power and Performance (SWaP). It is the successor to Niagara1, which is known in the market as the UltraSparcT1. This presentation will describe the Niagara2 design with special emphasis on its physical implementation.
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one x8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip with a die size of 342mm^2 is implemented in a 11M 65nm triple-Vt CMOS process.
BiographyUmesh Nawathe is currently a Senior Manager at Sun Microsystems responsible for circuit design and technology. Umesh has an MS(EE) from University of Michigan, Ann Arbor. He joined Sun Microsystems ~3.5 years back. Prior to that, Umesh held senior technical and management positions working for MIPS/Silicon Graphics designing MIPS processors and Intel before that.
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