Solid State Circuits Society

October 21, 2004

Our speaker was  Radu Zlatanovici (University of California at Berkeley, Ph.D. candidate), the topic of his presentation was
“ Power – Performance Optimization Methods for Digital Circuits“

Abstract

Most of today’s designs are power-limited yet performance is what ultimately sells products. Thus, it is interesting from a design standpoint to know how power and performance trade each other for digital circuits. The traditional way of designing digital circuits is to optimize for the best performance. Such an approach is not always appropriate in deep submicron technologies because targeting the ultimate performance usually results in prohibitive power consumption. It is therefore worthwhile to investigate how to reduce the power of a circuit without reducing its performance and, if still exceeding the power budget, how to further reduce the power with minimum performance penalty. In other words, it is worthwhile to investigate the optimal power – performance tradeoff curves of the circuits in order to make the best design decisions. Generating such optimal power-performance tradeoffs is a very broad problem due to the different definitions of “performance” at the different levels of the design. For a microprocessor, “performance” can mean “benchmark scores” at application level, “instructions per second” at architecture level, “cycle time” at micro-architecture (pipeline) level and “delay” at (combinational) circuit level. This talk discusses a methodology to generate power – performance tradeoffs at circuit and micro-architecture level. The design problem is formulated as an optimization problem, which is then solved using a mathematical optimizer. At circuit level the tool optimizes combinational circuits in the energy per transition – delay space. It computes the minimum achievable delay under maximum energy and correct operation constraints, by sizing the gates in the circuit. As an example, the tool is used to investigate energy – delay tradeoffs for 64-bit carry-lookahead adders, a very frequent critical path block and hotspot in high performance microprocessors. Conclusions are drawn about the optimal adder design in a given technology. The impact of additional design variables such as supply and threshold voltages is also discussed. At the next level of abstraction, (micro-architecture level) the tool optimizes pipelined circuits in the energy – cycle time space. It computes the minimum achievable cycle time under maximum energy and timing closure constraints. This version of the tool is still under development and it will be demonstrated on an IEEE-compliant Floating Point Unit (FPU). The presented optimization framework allows the designer to treat circuits’ power and performance not as two separate notions, but as the two sides of the same coin. The flow can then be used to explore the connection between the two sides, the optimal power – performance tradeoff curve.

Biography

Radu Zlatanovici received his B.S and M.S. degrees from Politehnica University Bucharest, Romania in 1999 and 2000 respectively. In 2000 he joined the University of California at Berkeley where he received an M.S. degree in 2002. He is currently working towards his PhD degree at the same university. In 1997 and 1998 he was a summer undergraduate researcher at the Institute of Microelectronic Systems of the Darmstadt University of Technology, Darmstad, Germany working on hierarchical macromodeling of analog circuits. He worked as an analog circuit designer at Semiconix Design, Bucharest, Romania from 1997 to 1999. He was on the faculty of Politehnica University Bucharest from 1999 to 2000. In 2002 and 2003 he interned at IBM T.J. Watson Research Center, Yorktown Heights, NY working on power – performance tradeoffs for pipelined digital circuits. He was a recipient of the Romanian Department of Education Excellence Fellowship in 1997-1999 and of the MobilRom Excellence Fellowship in 1998. He won the first prize at the Romanian National Design Contest for Analog Circuits in 1997,1998 and 1999. His current research interests include high-speed and low-power arithmetic circuits, design optimization in the power – performance space and the impact of novel devices such as FinFETs on the design of digital circuits.

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