Solid State Circuits Society

April 15, 2004

Our speakers were  Masoud Zargari and Manolis Terrovitis (Atheros Communications), and the topic of their presentation was:
“A Single-Chip, Dual-Band, Tri-Mode CMOS Transceiver for IEEE 802.11a/b/g Wireless LAN”.
Download:    Transceiver Presentation Frequency Synthesizer Presentation

The proliferation of multiple WLAN standards in the past few years has created the need for integrated, low cost, multi-mode multi-band transceivers. This presentation describes a single-chip dual band, tri-mode CMOS transceiver that implements the RF and analog front-end of an IEEE 802.11a/g/b wireless LAN standards.

The chip is integrated in a 0.25um standard CMOS process and occupies a total silicon area of 23mm square. The IC transmits 9dBm/8dBm EVM compliant output power at 5GHz/2.4GHz for a 64QAM OFDM signal. The overall receiver noise figure is 5.5/4.5dB at 5GHz/2.4GHz.

In the first part of presentation Massoud Zargari describes the architecture of the chip, insisting on the major blocks of the transceiver: LNA, selection filters, mixers, power amplifier, predrivers and the measured performance of the transceiver.

The transceiver operates in both 2.4 and 5GHz unlicensed frequency bands and has fully integrated transmit and receive channels. It includes on chip baseband GmC filters, synthesizer loop filters and VCOs. The dual-band relies heavily on reusing circuits blocks for different modes of operation to reduce the overall die size.

In the second part of the presentation Manolis Terrovitis describes the frequency synthesizer, a critical block of the WLAN transceiver and the design features applied in order to achieve good phase noise and spur performance necessary to insure high receiver sensitivity and low transmitter error-vector -magnitude required for the 64-QAM OFDM signals. It is a fully integrated integer-N PLL with programmable loop filter and on chip regulators. It uses switchable tuning capacitors in VCO to assure wide covering frequency range from 3.2-4GHz. The phase noise is -105dBc/Hz at 10KHz offset, and the spurs are below -64dBc when measured at the 5GHz transmitter output. The settling time is shorter than 150us. The block diagram of the synthesizer, the VCO topology, the high frequency divide-by-2 ,the charge pump and the synthesizer performance are presented.

Masoud Zargari received his M.Sc. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1993 and 1997 respectively. From 1996 to 1998 he was a member of the technical staff at Wireless Access Inc., Santa Clara, CA. where he worked on the design and development of wireless systems for two-way messaging networks. In 1998 he joined Atheros Communications as a member of the founding team where he is currently Director of analog design focusing on integrated systems for the IEEE 802.11 based wireless local area networks. During 1999 and 2000 Dr. Zargari was a consulting assistant professor at Stanford University where he taught courses in the area of RF and analog integrated circuit design.

Manolis Terrovitis obtained his diploma in engineering from the National Technical University of Athens, Greece in 1992 and his MS and PhD degrees from the University of California at Berkeley in 1996 and 2001 respectively. He held internship positions at Texas Instruments, Cadence Design Systems, and Philips Semiconductors. Since August of 2000 he has been with Atheros Communications working on analog RF and Mixed Signal circuits for wireless LAN applications.

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