Solid State Circuits Society

October 17, 2002

Our speaker was  Dr. Stefan Rusu, and the topic of his presentation was
“Trends and Challenges in Multi-Gigahertz Microprocessor Design”

Moore’s law drives the VLSI technology to smaller transistors and higher clock frequencies. As VLSI process features shrink deep into submicron territory, leading microprocessor designs are running at multi-GHz frequencies. This creates new challenges for designers at both the chip and the system level. This presentation will review the trends in microprocessor design and highlight the challenges ahead.

At the chip level, the metal interconnects are getting slower with every generation. Copper interconnects and low-K dielectrics will only temporarily ease the burden. To make up for this slowdown and still meet the increasing frequency targets, designers employ aggressive design techniques, like domino logic. This provides higher speed, but with a higher power dissipation. Another emerging technique for achieving higher frequencies is the use of dual-Vt transistors. The power supply voltage levels are dropping with every process generation, while capacitive and inductive coupling are becoming an increasing concern. Leading microprocessor designs include large on-die caches for improved performance. Clock distribution at multi-GHz frequencies is a challenge. The presentation will review techniques to control clock skew and jitter in modern processor designs. At the system level, bus interface speeds are increasing with every generation. The bus design is shifting from a common clock timing mode to a source-synchronous design that offers wider timing margins. Flip-chip packaging provides better power distribution and shorter interconnects.

Stefan Rusu is a Senior Principal Engineer in Intel’s Enterprise Products Group leading the technology and special circuits design team for the entire Itanium(R) Processor Family. He received an M.S. degree in Electrical Engineering from the Polytechnic Institute in Bucharest, Romania. He first joined Intel Corporation in 1984 working on data communications integrated circuits. In 1988 he joined Sun Microsystems working on microprocessor design with focus on clock and power distribution, packaging, standard cell libraries, CAD and circuit design methodologies. He re-joined Intel Corporation in 1996 to drive the clock and power distribution, cell library, I/O buffers and package design for the first Itanium(R) processor. His technical interests are high-speed clocking, power distribution, I/O interfaces, low-power design and high-speed circuit design techniques. He has published numerous technical papers and currently holds 13 U.S. patents with several more pending. He is a Senior Member of the IEEE and has been a member of the ESSCIRC Technical Program Committee since 1998.

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