Upcoming IEEE SoCal Nanotechnology Council Chapter Seminar


This Chapter organized and is sponsoring the IEEE Student Engineering Team Challenge. 

Find details at https://ieeesetc.org/   The Student Team Projects will be presented 9/3/2021 and 9/4/2021

The IEEE Student Engineering Team Challenge (IEEE SETC) is focused on students from socio-economic disadvantaged communities with the goal to stimulate interest in the STEM fields. This challenge is actively looking to include minority children of color. These students are invited to participate, along with a few of their peers, in this poster competition by displaying an original project proposal focused on a few targeted topics.

Students in High School and College considering College majors in science and engineering disciplines are encouraged to try their hand at meeting this team challenge by designing and displaying a solution for or an investigation into a problem area associated with one of the topical boundaries of this year’s challenge.

For some of the topical areas startup training and materials may be available. For projects that rise to the top of the challenge more equipment and support may be made available to foster completion of the proposal. IEEE Student Members may be available to train and assist as well.

Team projects that are inclusive and collaborative showcasing creativity and ingenuity will be shared with an audience of academic and industrial technical experts who will provide recognition and award prizes in several participant categories. Also your poster may be published in an IEEE Society publication and you can note your participation on your resumes and college applications.


Past IEEE SoCal Nanotechnology Council Chapter Seminars


Date: November 17, 2020    Location: On – Line at   

Topic: Toward 100Gbps Fully Integrated Wireless Communication Transceivers

Speaker: Dr. Huan Wang, Qualcomm


The IEEE Foothill / Orange County Joint Sections Nanotechnology Council (NTC) Chapter and IEEE Foothill CPP Student Chapter held its Fourth event on November 17, 2020 on line and at Cal Poly Pomona. The keynote speaker was Dr. Huan Wang who recently completed his Doctorate at UCI and is now working at Qualcomm on analog/RF IC design for wireless cellular communication.

Dr. Wang described how his work has led to the design of a wireless communication link capable of 100 Gps with simpler data modulation schemes using lower power. A circuit design fabricated at the sub 100 nanometer scale with Silicon Germanium technology has been completed to demonstrate his results. Much of the circuits operation is in the analog domain taking advantage of the SiGe NPN Bipolar transistor amplifier’s very high maximum operating frequency as the key enabler. This breakthrough promises to streamline data centers by replacing lower speed high energy consuming wired interconnects with low power high speed wireless transceiver links.

The audience included many CPP students who said they had gained valuable information from this event. The event was held on Zoom with 35 attendees and hosted by Adrian Alarcon, President of the IEEE Student Chapter.


The future’s more connected societies are in sore need of high-speed point-to-point wireless links with a data rate comparable to wireline links in both indoor short-range and outdoor long-range scenarios. Enabling applications include: optical fiber replacement, high-capacity backhauls, close-proximity wireless data transfer, etc. High-speed communication relies on two major factors: bandwidth and modulation format. The vastly under-utilized mm-wave to sub-THz band is very attractive for this application. However, the abundance of bandwidth in mm-wave/sub-THz bands cannot be easily utilized with commercially available low-cost Silicon-based fabrication technologies. Meanwhile, increasing modulation order puts stringent requirement on the high-speed mixed-signal interface design, i.e. analog-to-digital converters, digital-to-analog-converters and digital signal processors. In short, conventional transceiver architectures encounter serious bottleneck that limits achievable data rate and posts significant concerns on system cost and efficiency. The state-of-the-art solutions will be presented and discussed first, followed by our proposed way of implementing highly integrated ultra-high-speed wireless transceivers.


Huan Wang received his B.S. degree from Zhejiang University, Hangzhou, China, in 2011; M.S. degree from The University of Texas at Austin, Austin, Texas, USA, in 2013 and Ph.D degree from University of California, Irvine, CA, USA in 2020, all in Electrical Engineering. From 2013 to 2015, he was with Cirrus Logic, Austin, Texas, as an analog design engineer, where he was involved in the design of audio class-D amplifiers for mobile applications. He was an engineering intern with Qualcomm during the summer of 2012, 2016 and 2019. He is now with Qualcomm, San Diego, working on analog/RF IC design for wireless cellular communication. His research interest includes analog, RF and mm-wave/THz circuits and system design. 

Date: November 15, 2019

Location: TowerJazz Semiconductor Newport Beach CA

Event: Semiconductor Fabrication Foundry Tour

The group of 16 mainly consisted of students currently taking a VLSI Circuit Design or Nanotechnology course who were interested in the fabrication process of semiconductor devices.

Upon arrival, the students were greeted by Cal Poly Pomona adjunct professor and TowerJazz engineer senior Michael Jue, who kindly helped arrange the tour for the students. Before the tour, the students were given a technical speech by Victer Chan who is also a TowerJazz engineer. The talk detailed what types of semiconductor technologies were currently dominating the market and also how TowerJazz contributes to specific processes and their corresponding applications. Mr. Chan discussed how as communication systems become faster and more advance, the technology used to implement chips must adapt as well.

After the presentation, the students then split into two groups and received a window tour of the foundry. The tour went in depth about each step of the semiconductor manufacturing process. VLSI students were able to easily point out steps that were covered in their lecture, the most identifiable being photolithography. Because this step in the manufacturing process is quite sensitive, the photolithography room only uses a special shade of yellow light with a wavelength that won’t interfere with the devices. The whole foundry must operate in a clean room as to minimize any potential source of contamination. Students were introduced to the rigorous requirements of keeping a cleanroom, and how every employee must “suit-up” before entering the foundry.

After the tour, students were introduced to the TowerJazz human resource department, where they were encouraged to apply for an internship or full-time position upon graduation.


Date: April 18, 2019              Time: 6:30PM Networking and Pizza; 7PM Presentation

Location: California State Polytechnic University, Pomona, Building 9 Room 409

Topic: Smart Optical Materials by Nanoscale Assembly

Speaker: Dr. Yadong Yin, Professor of Chemistry, University of California Riverside

Smart materials hold great promises for many intrigue applications as they exhibit chemical and physical responses to the applied external stimuli. This presentation will focus on nanostructured materials with responsive optical properties that can find applications in printing, sensing, signage, security documents, and displays. We will discuss our recent progress on the development of chemical and assembly approaches for the fabrication of various nanostructured materials whose optical properties can be dynamically tuned by controlling the spatial arrangement of the nanoscale building blocks. We show that many novel optical materials could be developed by manipulating the diffraction, refraction, birefringence, and electronic resonances through controlling the interaction between light and the nanostructures.

Prof. Yadong Yin received his B.S. (1996) and M.S. (1998) in Chemistry from the University of Science and Technology of China, and Ph.D. (2002) from the University of Washington, Seattle (with Prof. Younan Xia). In 2003 he became a postdoctoral fellow at the University of California, Berkeley under the supervision of Prof. A. Paul Alivisatos, and then a staff scientist at Lawrence Berkeley National Laboratory in 2005. He joined the faculty at the Department of Chemistry, University of California, Riverside as an Assistant Professor in 2006, and then he was promoted to Full Professor in 2014. His recent recognitions include Cottrell Scholar Award (2009), DuPont Young Professor Grant (2010), 3M Nontenured Faculty Grant (2010), NSF CAREER award (2010), and NML Researcher Award (2016). He is currently an associate editor of the Journal of Materials Chemistry C, and also serves on the editorial board for NPG Asia Materials, Advanced Functional Materials, SCIENCE CHINA Materials, ChemNanoMat, Research, and Chem. Rev.

All Students & the Public Are Welcome. This event is FREE.

Please RSVP to ensure enough food is ordered at: IEEE vTools

Driving Directions at: Drive to CPP

Parking Directions: We reserved parking passes at the campus parking booth near the parking structure near the campus police department. Use these coordinates 34.060584, -117.815547 in Bing or Google Maps to help you navigate to our campus. At the parking booth you can ask for directions to building 9 and where the pass is valid but the 4-story structure nearby is where they will normally have you park.

The map linked above is in general good except that the Visitors Information Booth is no longer located close to parking lot C, but is now located at F9.

Date: January 30, 2019        

Topic: Nano-Photonics, Plasmonics, and the Memristor

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Speaker: Dr. Wei Wu, Associate Professor of Electrical Engineering, University of Southern California

Abstract: Dr. Wu presented on recent progress in three areas of nanotechnology: nano-photonics, plasmonics. In nanophotonics, he described an optical metasurface for color-reflective displays. In plasmonics, he presented a new technology based on collapsible nanofingers to fabricate plasmonics structures with atomic precision, over large areas with high reliability and repeatability. Based on this technology, he studied quantum tunneling in gap plasmons and demonstrated label-free single molecule sensing with SERS.

Bio: Dr.Wu received with a BS in Physics from Peking University, and a Ph.D. in Electrical Engineering from Princeton University in 2003. Before joining USC in 2012 he worked as Senior Scientist at HP labs. His work includes nanoimprint lithography and applications in nano-electronics, nano-photonics, plasmonics, chemical sensing and nano-electrochemical cells. He coauthored 101 peer reviewed journal papers, 2 book chapters and more than 100 conference presentations, including 16 keynote and invited presentations. He has 115 issued U.S. patents. He is the chair of Nanofabrication track, IEEE Nanotechnology Council. He is a co-editor of Applied Physics and an associate editor of IEEE Transactions on Nanotechnology. He was also an IEEE Nanotechnology Council 2015 and 2016 Distinguished Lecturer.

Location: Cal State University Fullerton, Building TSU. Room HETEBRINK-AB



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