Time & Date:  6pm-8:30pm  June 1, 2015
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Venue:   KeyPoint Credit Union
2805 Bowers Ave (just off Central Expressway)
Santa Clara, CA 95051

Park in lot adjacent to building  on Bowers Ave.

Note of Appreciation:  IEEE SV Tech History committee is extremely grateful to KeyPoint Credit Union for use of their auditorium as our prime venue.   Many thanks to Doron Noyman of KeyPoint for his support in making that happen.
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Abstract:

Electronic Design Automation (EDA) for LSI/VLSI Integrated Circuits not only helped meet the challenge of designing systems on a chip (SoC), but also played a crucial enabling role in development of the fabless model that’s so pervasive in today’s semiconductor industry.  EDA allowed system engineers to design chips and gave companies flexibility in targeting an IC design to available semiconductor fabs for manufacturing LSI and VLSI chips.

Companies like Cirrus Logic, Chips & Technologies, and Xilinx were among the first to “truly” separate the design of chips from their manufacturing in the mid 1980’s.  Prior to that time, each semiconductor company had their own silicon waver fabrication plant(s).  Both small and large leading edge semiconductor companies exploit the fabless semiconductor business model today.

This panel will recount the developments in EDA that took place from mid 1970’s to end of 1980’s and share with the audience their insights into how EDA helped transform the semiconductor industry into the fabless semiconductor mode.

Panelists:  

  • Suhas Patil, Cirrus Logic
  • Aart de Geus, Synopsys
  • Doug Fairbairn, VLSI Technology

Panel Moderator:   Alan J Weissberger, Chair-IEEE SV Tech History Committee

Bio’s of Panelists:

1. Suhas S. Patil, ScD EE

Suhas Patil is founder and retired Chairman of Cirrus Logic, Inc. a leading semiconductor company in US. He is co-founder of The Indus Entrepreneurs (TIE) world’s largest nonprofit for fostering entrepreneurs and served as its founding president.

Before becoming an entrepreneur, Dr. Patil was Assistant Professor of Electrical Engineering (EE) at MIT where from 1972 to 1974 he also served as Assistant Director of Project MAC (Multi-Access Computer), where leading edge work was done on time-sharing and on line computer systems.  In 1966 Prof. Patil developed one of the first on line information management systems for the department of Electrical Engineering at MIT.   From 1975 to 1980 Dr. Patil was an Associate Professor of Computer Science at University of Utah where he started the VLSI (very large-scale integrated circuits) group and worked on design methodology for design of complex integrated circuits.

In 1980 Dr. Patil started Patil Systems, Inc. a semiconductor company based on his academic work in design automation of IC. In 1984 this company moved to Silicon Valley from Salt Lake City, Utah and changed its name to Cirrus Logic, Inc. High volume commercial SoC chips for set top units developed at Patil Systems, Inc. in early 1980 showed viability the fabless model of semiconductor industry.

Suhas received the Doctor of Science degree (ScD) in Electrical Engineering from MIT in 1970.  In 1995 Indian Institute of Technology (IIT), Kharagpur conferred Honorary Doctor of Science degree on Suhas for his work in science and industry.  He served on the board of trustee of The Computer History Museum, The Tech and the World Affairs Council of Northern California from. In February, 2003 Dr Patil was named Life Fellow of Indian Institute of Technology, Kharagpur.

2.  Aart de Geus, PhD EE

Aart de Geus is the founder, chairman and CEO of Synopsys Inc. He is a fellow of the IEEE and a Phil Kaufman Award award winner.  Aart received  a PhD in EE from Southern Methodist University, Texas, USA.

Since co-founding Synopsys in 1986, Dr. de Geus has expanded Synopsys from a start-up synthesis company to a global high tech leader. Long considered a pioneer in our industry, he’s been recognized for his technical, business and community achievements with multiple awards, including Electronic Business Magazine’s “CEO of the Year,” the IEEE Robert N. Noyce Medal, the GSA Morris Chang Exemplary Leadership Award, the Silicon Valley Engineering Council Hall of Fame Award, and the SVLG Life-time Achievement Award. He serves on the Boards of the Silicon Valley Leadership Group, Applied Materials, the Global Semiconductor Alliance, and the Electronic Design Automation Consortium.

3.  Doug Fairbairn, MSEE

Doug Fairbairn is Staff Director at the Computer History Museum and also his own photography business – Douglas Fairbairn Photography.   Doug earned a BS/MSEE at Stanford in 1971.  After graduation, Doug joined Xerox PARC as a systems engineer. While at PARC, he teamed up with Carver Mead and Lynn Conway to help develop the Mead Conway VLSI design methodology.

Leveraging that work, he formed VLSI Design Magazine (Lambda at the time) and was a co-founder of VLSI Technology in 1980. At VLSI Doug managed its leading edge IC design tools and ASIC business units.

Doug left VLSI in 1990 to form Redwood Design Automation and was later a division manager at Cadence after its purchase of Redwood in 1994.  Since leaving Cadence in 1998, he has served on the Boards of Catalytic, Quickfilter, Simutech, and Verisity.  He joined CHM and formed his photography business in 2006.

About the Moderator:

Alan J Weissberger, ScD EE was hired by Fairchild Systems Technology in March of 1970 to work on CAD algorithms and software to automate the layout of printed circuit boards.  Fairchild wanted to sell such a tool to its semiconductor customers and use it internally for its Sentry IC Tester and the family of 8, 16, and 32 bit minicomputers (known internally as Sprint) it was developing at that time.  In Sept 1970 the minicomputer division was shut down and Weissberger was laid off without ever working on the CAD project.

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Time-line (for all our meetings held at KeyPoint):

6pm-6:30pm:        Networking and light dinner/non-alcoholic drinks ($5 donation requested)
6:30pm-6:35pm:   Opening Remarks & Introductions
6:35pm-8pm:        Panel Discussion
8pm-8:15pm:        Audience Q & A
8:15pm:                Appreciation & Adjournment; informal chit-chat with panelists
8:30pm:                Everyone must be out of the auditorium
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REGISTRATION REQUIRED:  Click here to register.

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Invitation to ask a question or comment:

If you’d like to submit a question or issue to discuss during the panel, please send email to: alan.weissberger@ieee.org  OR leave a comment in the box below this post.  There will be ~15 minutes for audience Q&A at the end of our panel discussion.