The  IEEE Milestone Award event recognizing the technological achievement of the SPARC RISC Architecture will be presented at 10am on Feb 13, 2015 at the Oracle Auditorium in Santa Clara, CA.   That’s one day after the UC Berkeley RISC Project milestone is presented as described in the previous post.   The plaque unveiling will be preceded by a dedication ceremony in the Oracle Auditorium beginning at 10:00 am with Bill Joy, Dave Patterson, Andy Bechtolsheim, all instrumental in the early success of the SPARC architecture, listed as planned speakers. IEEE President Howard Michel will also say a few words.  Over 200 IT professionals from throughout the Silicon Valley and beyond are expected to attend.

The Relevance of the SPARC Processor Architecture:

Sun Microsystems introduced SPARC (Scalable Processor Architecture) RISC (Reduced Instruction-Set Computing) in 1987. Building upon UC Berkeley RISC and Sun compiler and operating system developments, SPARC architecture was highly adaptable to evolving semiconductor, software, and system technology and user needs. Over the course of its life the SPARC processor architecture has powered millions of servers and workstations and is still a leading and highly valued technology. Today, Oracle continues to engineer new levels of excellence into the SPARC architecture delivering the highest performance scalable servers, for engineering, enterprise, Internet and cloud computing applications

The first SPARC processor debuted in 1986 and was the CPU for the Sun-4 workstation the following year. In 1992 Sun launched its first high-end SPARC server, the successful SPARCcenter 2000. Today, the SPARC processor family is used in Oracle’s enterprise servers to create architectures that are optimized for a powerful mix of application types, from CRM systems and Java/Web middleware infrastructure applications to mission-critical ERP and back-end OLTP/data warehousing enterprise applications that depend on high availability and scalability.

According to Wikipedia,  there have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit “extended precision” floating-point arithmetic to 128-bit “quad-precision” arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture.  SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation, Fujitsu, ICL, LSI Logic, Matsushita, Philips, Ross Technology, Sun Microsystems, and Texas Instruments.

A very interesting post titled SPARC History from 1987 to 2010 provides more history and background information.

You can register for the Feb 13th event here.