Silicon Valley Area Chapter

(SCV, SF, OEB)

AI is Accelerating the Shift to Advanced Packaging with PLP and Glass Cores 🗓

-- advance packaging, heterogeneous integration, thermal management, systems, data-centers, glass core, interposer, warpage ...

Organized by the Binghamton EPS Chapter
Speaker: Yik Yee (YY) Tan PhD, Principal Technology & Market Analyst, Yole Group
Meeting Date: Thursday, February 26, 2026
Time: Checkin via WebEx at 8:50 AM; Presentation at 9:00 AM (PST)
Cost: none
Reservations: ieee.webex.com/weblink/register
Summary: The semiconductor sector continues to expand rapidly, supported by growing needs in AI, automotive electronics, and consumer devices. As the limits of traditional scaling become increasingly evident both physically and economically, advanced packaging is taking center stage as a critical driver of higher performance, tighter integration, and further miniaturization. In this context, next-generation packaging platforms such as panel-level packaging (PLP) and glass core substrates are emerging as key technologies shaping the industry’s future direction.
PLP is gaining industry interest for its potential to reduce manufacturing costs and support ultra-large form-factor packages. Nevertheless, its adoption introduces several materials and process challenges, including warpage management, thermal robustness, and process compatibility. To overcome the warpage issue, alternative material like glass core substrate is being explored for its exceptional dimensional stability and favorable electrical characteristics. Despite advantages, the use of glass raises practical concerns in handling, via creation, and integration within existing assembly infrastructures.
This presentation will delve into these evolving technology pathways, examining market motivations, supply-chain considerations, and the broader ecosystem shifts surrounding them. It will outline both the opportunities these solutions present and the technical barriers that must be overcome as advanced packaging moves into its next phase of development.
Bio: Yik Yee (YY) Tan Ph.D. is a Principal Technology & Market Analyst, Semiconductor Packaging & Assembly at Yole Group. Dr. Tan holds a Ph.D. in Engineering from Multimedia University (MMU, Malaysia). She has more than 25 years of experience in semiconductor packaging. Based on her technical expertise and market knowledge, she develops technology & market reports and is engaged in dedicated custom projects. Prior to Yole, Dr. Tan worked as a failure analyst and interconnect champion at Infineon Technologies (Malaysia) and later as an open innovation senior manager at Onsemi (Malaysia). She has published more than 30 papers and hold 4 patents and is the award winner for IEEE EPS – Regional 10 Contribution Award 2024 and IEEE Malaysia Section – Outstanding Industry Volunteer Award 2024.

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