Abstract: Semiconductor Tool maintenance is a complex task due to process complexity, process integration challenges, and customer requirements. Historically, maintenance strategies have been reactive due to these complexities. Applied Materials has been focused on moving from a generally reactive method of reacting to tool issues to prescriptive methods of maintaining process equipment. This migration is through a combination of advanced anomaly detection techniques which provide low false positives, methods of translating fail modes into Reactive Useful Life estimates and ultimately prescribing solutions to issues in advance using Generative Artificial Intelligence. This discussion will cover some of the challenges and solutions to this framework. Speaker(s): Mike, Agenda: 6:00 - 6:30 - Networking and light dinner (for in person attendees) 6:30 - 7:30 - Talk and Q & A 7:30 - 8:00 - Wrap up and Networking Room: SCDI 4010, Bldg: Sobrato Campus for Discovery and Innovation, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95053, Virtual: https://events.vtools.ieee.org/m/506966

[] Speaker(s): Noah Room: 112, Bldg: Heafey, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95053

ABSTRACT Digital twin (DT) is a relatively new technology concept with potential to improve semiconductor wafer processing. Development of this technology has been evolutionary and a direct result of the confluence of advances in high-performance computing, network communication, optimization techniques, sensing technologies and the use of vast array of sensors for process monitoring. Potential application of DT technology to semiconductor equipment includes predictive maintenance, fault detection, performance evaluation, and chamber matching. Following a discussion of the DT concept, this talk will focus on SC’s experience with the most challenging aspect of DT technology – development of fast subsystem models that may be subsequently integrated to create a digital twin of a system. In most cases, these low-order models have been developed from high-order, high-fidelity physical models whose simulations run too slow for DT application. SC has an extensive background and experience in using various model-order reduction techniques to develop such fast models of various semiconductor equipment such as RTP, plasma etch, CMP, and bake lithography systems. SC has successfully used these models for closed-loop real time process control, virtual sensing, and chamber matching. Additionally, we describe a couple of our research projects on non-manufacturing applications that are relevant. In one, a low-order model of a complex system was developed by combining physics-based modeling with machine learning (deep neural network, or DNN) so that the user would be warned when changes to the system warranted that the DNN be retrained. In another project, a complete DT of a large structural system was developed that is still in operation. Speaker(s): Abbas Agenda: 6:00 - 6:30 - Networking and light dinner (for in person attendees) 6:30 - 7:30 - Talk and Q & A 7:30 - 8:00 - Wrap up and Networking Room: 3116, Bldg: SCDI, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95053, Virtual: https://events.vtools.ieee.org/m/475484