IEEE EPS Phoenix Section Chapter, EP21

Title: Using Architectural Simulation to investigate Chiplets for Scalable and Cost Effective HPC Beyond Exascale Abstract: Chiplets have become a compelling approach to scaling and heterogeneous integration e.g. integrating workload-specific processors and massive bandwidth memory systems into computing systems; integrating die from multiple function-optimized process nodes into one product; integrating silicon from multiple businesses into one product.  Chiplet-based products have been produced in high volume by multiple companies using proprietary chiplet ecosystems. Recently, the community has proposed several new standards (e.g., UCIe) to facilitate integration and interoperability of any compliant chiplet. Hyperscalers (e.g., Google, Amazon) are actively designing high volume products with chiplets through these open interfaces. Other communities are exploring the end-to-end workflow and tooling to assemble chiplet-based products. High performance computing can benefit from this trend. However, the performance, power, and thermal requirements unique to HPC, present many challenges to realizing a vision for affordable, modular HPC using this new approach.  Architectural modeling and simulation will play a critical role in pathfinding for this new potential direction for HPC beyond Exascale. Biography: John Shalf is the Department Head for Computer Science at Lawrence Berkeley National Laboratory.  He also formerly served as the Deputy Director for Hardware Technology on the US Department of Energy (DOE)-led Exascale Computing Project (ECP) before he returned to his department head position at LBNL. He has co-authored over 100 peer-reviewed publications in parallel computing software and HPC technology, including the widely cited report “The Landscape of Parallel Computing Research: A View from Berkeley” (with David Patterson and others). He is also the 2024-2027 distinguished lecturer for the IEEE Electronics Packaging Society.  Before joining Berkeley Laboratory, John worked at the National Center for Supercomputing Applications and the Max Planck Institute for Gravitation Physics/Albert Einstein Institute (AEI), where he co-created the Cactus Computational Toolkit. Agenda: Refreshments: 5:30-6:00pm Seminar Talk: 6:00-7:00pm MTW Tour: 7:00-7:30pm

Title: Challenges and Solutions for High-Speed Signaling in Future System-in-Packages Abstract: With the rapid developments in artificial intelligence and other high performance computing applications, future electronic systems need to provide significantly improved performance. One area where the performance demand has been scaling very aggressively is for interconnecting different components and chiplets by means of system-in-packages with high-speed/high-bandwidth signaling. To address this demand, future system-in-package architectures and designs require innovations in package technologies, analysis and validation methods and tools, and standardization. This presentation will review some recent developments in advanced electronic packaging technologies that aim to provide significantly improved performance for both on- and off-package high-speed interconnects. It will also summarize some of the current challenges and solutions for the corresponding electrical methodologies and metrologies. Finally, recent progress on standardization of on-package high-speed signaling for seamless 2/2.5/3D integration of chiplets will be presented with some thoughts on future scaling and remaining challenges.  Bio: Kemal Aygün is a Fellow at Intel Foundry Technology Development organization, where he has been leading the development of high-bandwidth package and socket technologies and modeling and characterization methodologies for on- and off-package I/O interfaces. He has co-authored 5 book chapters, more than 100 journal and conference publications, and holds 180 patents. He was the General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems Conference. Dr. Aygün is an IEEE Fellow and has been acting as a Distinguished Lecturer for the IEEE Electronics Packaging Society. He has a Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign. Location: Intel CH6 (5000 W Chandler Blvd, Chandler, AZ 85226, https://maps.app.goo.gl/F79rqnXS4k3EnakWA) Date: May 22, 2025 Agenda: Refreshments: 4:00-4:30pm Seminar Talk: 4:30-5:30pm